AVANEESH KUMAR DUBEY

@gmail.com

Visiting Faculty, ECED
MNNIT ALLAHABAD



                         

http://researchid.co/akd8292

EDUCATION

PH.D., ECED, MNNIT ALLAHABAD, PRAYAGRAJ

RESEARCH INTERESTS

LOW POWER VLSI, ANALOG/DIGITAL CIRCUITS, MIXED-SIGNAL CIRCUITS

9

Scopus Publications

25

Google Scholar Citations

3

Google Scholar h-index

Scopus Publications

RECENT SCHOLAR PUBLICATIONS

  • Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage
    AK Dubey, RK Nagaria
    Analog Integrated Circuits and Signal Processing, 1-11 2019

  • Design and Performance of High-speed Low-Offset CMOS Double-Tail Dynamic Comparators using Offset Control scheme
    Avaneesh K. Dubey, Vikrant Varshney, Pratosh k. Pal, Ankur Kumar, R. K. Nagaria
    The 9th Annual Information Technology, Electromechanical Engineering and 2019

  • Enhanced Gain Low-Power CMOS Amplifiers: A Novel Design Approach Using Bulk-Driven Load and Introduction to GACOBA Technique
    AK Dubey, RK Nagaria
    Journal of Circuits, Systems and Computers 27 (13), 1850204 2018

  • A Modified High Speed Domino with Low Leakage for Wide Fan-in Domino OR-Gate
    Ankur Kumar, Pratosh Kumar Pal, Avaneesh Kumar Dubey, Vikrant Varshney, R K ...
    2018 15th IEEE India Council International Conference (INDICON) - Circuits 2018

  • A 0.55V, 28.6ppm/ o C Nanopower Subthreshold Voltage Reference with Body Biasing
    Pratosh Kumar Pal, Avaneesh Kumar Dubey, Ankur Kumar, Vikrant Varshney, R K ...
    2018 15th IEEE India Council International Conference (INDICON) - Circuits 2018

  • Design of Power Efficient Low-Offset Dynamic Latch Comparator using 90nm CMOS Process
    V Varshney, AK Dubey, A Kumar, PK Pal, RK Nagaria
    2018 3rd International Innovative Applications of Computational Intelligence 2018

  • Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect
    AK Dubey, RK Nagaria
    Journal of Circuits, Systems and Computers, 1950157 2018

  • Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load
    AK Dubey, RK Nagaria
    Microelectronics Journal 78 (August 2018), 1-10 2018

  • Design of Power Efficient Low-Offset Dynamic Latch Comparator using 90nm CMOS Process
    Vikrant Varshney, Avaneesh K. Dubey, Pratosh k. Pal, Ankur Kumar, R. K. Nagaria
    3rd IEEE International Conference on Innovative Applications of 2018

  • Design of low-power high-speed double-tail dynamic CMOS comparator using novel latch structure
    R Jain, AK Dubey, V Varshney, RK Nagaria
    2017 4th IEEE Uttar Pradesh Section International Conference on Electrical 2017

  • Voltage comparison based high speed & low power domino circuit for wide fan-in gates
    PK Pal, AK Dubey, SR Kassa, RK Nagaria
    2016 IEEE International Conference on Electron Devices and Solid-State 2016

  • Enhanced slew rate, constant-gmrail-to-rail OpAmp using 1:2 current mirror biasing technique
    AK Dubey, RK Nagaria, PK Pal, RK Singh
    2016 International Conference on Computing, Communication and Automation 2016

  • Logical Effort Method for Dynamic Power and Delay Estimation of Multi-Threshold CMOS and Its Application in Low Power VLSI
    A Kumar, SR Kassa, AK Dubey, RK Nagaria, RK Singh
    International Conference on Advance Computational Technique in Information 2016

  • Efficient technique to reduce power dissipation of Op-Amps at high speed
    AK Dubey, P Srivastava, M Pattanaik
    2015 International Conference on Robotics, Automation, Control and Embedded 2015

  • Low Power, Accurate Variable Gain Amplifier (VGA) with High dB-Linear Gain at 900 MHz
    AK Dubey, P Srivastava, M Pattanaik
    International Journal on Advance Research in Electrical and Electronics 2015

MOST CITED SCHOLAR PUBLICATIONS

  • Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load
    AK Dubey, RK Nagaria
    Microelectronics Journal 78 (August 2018), 1-10 2018
    Citations: 7

  • Enhanced Gain Low-Power CMOS Amplifiers: A Novel Design Approach Using Bulk-Driven Load and Introduction to GACOBA Technique
    AK Dubey, RK Nagaria
    Journal of Circuits, Systems and Computers 27 (13), 1850204 2018
    Citations: 5

  • Design of low-power high-speed double-tail dynamic CMOS comparator using novel latch structure
    R Jain, AK Dubey, V Varshney, RK Nagaria
    2017 4th IEEE Uttar Pradesh Section International Conference on Electrical 2017
    Citations: 5

  • Efficient technique to reduce power dissipation of Op-Amps at high speed
    AK Dubey, P Srivastava, M Pattanaik
    2015 International Conference on Robotics, Automation, Control and Embedded 2015
    Citations: 3

  • Voltage comparison based high speed & low power domino circuit for wide fan-in gates
    PK Pal, AK Dubey, SR Kassa, RK Nagaria
    2016 IEEE International Conference on Electron Devices and Solid-State 2016
    Citations: 2

  • Low Power, Accurate Variable Gain Amplifier (VGA) with High dB-Linear Gain at 900 MHz
    AK Dubey, P Srivastava, M Pattanaik
    International Journal on Advance Research in Electrical and Electronics 2015
    Citations: 2

  • Enhanced slew rate, constant-gmrail-to-rail OpAmp using 1:2 current mirror biasing technique
    AK Dubey, RK Nagaria, PK Pal, RK Singh
    2016 International Conference on Computing, Communication and Automation 2016
    Citations: 1