AVANEESH KUMAR DUBEY
@mnnit.ac.in
Visiting Faculty, ECED
MNNIT ALLAHABAD
EDUCATION
PH.D., ECED, MNNIT ALLAHABAD, PRAYAGRAJ
RESEARCH INTERESTS
LOW POWER VLSI, ANALOG/DIGITAL CIRCUITS, MIXED-SIGNAL CIRCUITS
Scopus Publications
Scholar Citations
Scholar h-index
Scholar i10-index
Scopus Publications
Hena Shivhare, Avaneesh Kumar Dubey, and Sumit Kumar Jha
Springer Nature Singapore
Avaneesh Kumar Dubey, Vikrant Varshney, Ankur Kumar, Pratosh Kumar Pal, and Rajendra Kumar Nagaria
Springer Singapore
Pratosh Kumar Pal, Avaneesh Kumar Dubey, Rajeev Kumar Chauhan, and Rajendra Kumar Nagaria
Springer Singapore
Vikrant Varshney, Avaneesh K. Dubey, and R. K. Nagaria
World Scientific Pub Co Pte Lt
The need of energy-efficient, high-speed, and low-offset analog-to-digital converters is forcing to design the dynamic latch comparators to enhance the speed and energy efficiency with minimum offset. This paper presents a novel double tail dynamic latch comparator using bulk-driven process and common-gate (CG) amplifier in amplification stage. The gain of amplification stage is enhanced using GACOBA load in which gain is controlled by bulk amplification through CG amplifier. It results in remarkable enhancement in regeneration speed and reduction in power consumption. The analytical expressions of delay and offset due to mismatch are also derived. These derivations explore the key contributors to reduce the delay and offset of proposed comparator. The outcomes are verified in CADENCE SPECTRE at 45-nm CMOS process technology through various simulations and Monte-Carlo analysis at different process corners. The post-layout analysis validates the simulation results. The proposed comparator is 93% more energy-efficient and lessens more than 84% delay in comparison of conventional design. The 1–[Formula: see text] input offset voltage and average input voltage error due to kickback noise are 2.48[Formula: see text]mV and 0.824[Formula: see text][Formula: see text]V, respectively at 0.8[Formula: see text]V power supply with 34.32[Formula: see text][Formula: see text]m2 active area.
Ankur Kumar, Pratosh K. Pal, Vikrant Varshney, Avaneesh K. Dubey, and R. K. Nagaria
Springer Singapore
A leakage-tolerant low-power wide fan-in OR logic domino circuit is presented to decrease the leakage current and to enhance the noise immunity. Primarily, an efficient switching control in keeper network is developed to reduce the switching of keeper transistor in both phases, so that dynamic power and noise immunity can be improved. Further, a diode-connected NMOS transistor in evaluation network is incorporated in series with the footer transistor of standard domino circuits. This significantly decreases the leakage current and charge sharing because of the stacking effect. This reduction in leakage and charge sharing ensures the improvement in the noise margin. Furthermore, a current mirror and feedback NMOS transistors are also employed in the evaluation network to improve the speed of the circuit and fully discharge the dynamic node. The simulation results of proposed domino and reported domino circuits are designed using Spectre simulator under cadence virtuoso models of 45-nm technology which shows the 31% reduction in power dissipation (PD) and 1.53 times improvement in noise immunity at the similar delay compared to the standard domino circuits.
Avaneesh K. Dubey, Vikrant Varshney, Ankur Kumar, Pratosh K. Pal, and R. K. Nagaria
Springer Singapore
Keshav Kumar Mishra, Avaneesh K. Dubey, Vikrant Varshney, and Kamal Prakash Pandey
IEEE
In this paper, an energy efficient novel hybrid-CMOS 1-bit Full Adder based on XNOR-XNOR logic is presented. The proposed full adder is designed with 16 transistors, whereas the novel full swing XNOR logic is implemented using 5 transistors. The proposed hybrid full adder is designed in Cadence Virtuoso and the simulation work is carried out in Spectre simulator at $45nm$ technology node and 0.8V of power supply. The proposed work has been compared with recent reported work based on several hybrid design style. The propagation delay, power dissipation and energy consumption are 207.2pS, 45.32nW and 9.39aJ respectively for the proposed hybrid full adder. Addition to these, the effect of process and temperature variation has been analyzed. The novel full swing XNOR helps to improve the nose margin of the proposed HFA. A 4-bit binary adder is also implemented using the proposed 1-bit hybrid full adder for the purpose of test and verification. The propagation delay and power dissipation are 551pS and 168.83nW respectively for the 4-bit binary adder.
Avaneesh K. Dubey, Pratosh K. Pal, Vikrant Varshney, Ankur Kumar, and R. K. Nagaria
IEEE
This study presents the behavior of fully depleted silicon-on-insulator (FD-SOI) MOSFET by variation of channel doping concentration and work function of gate material. The channel doping concentration and work function of gate material are varied from 1012to 1019 cm-3and 4.4 to 4.8eV respectively. The investigation is presented for 5nm of silicon film thickness with 2nm and 5nm thickness of gate oxide and buried oxide (BOX) respectively. The comparative study of doping variation on several performance parameters has been characterized using Visual TCAD EDA Tool. The result shows that there is very sharp rise or fall in the device parameters value at very high doping (1019 cm-3), The required tuning of off current is also possible with respect to these variations as the 81 % sudden drop is noticed for 10 times increment in doping concentration from 1017 cm-3and at work function of 4.6eV.
Vikrant Varshney, Ankur Kumar, Avaneesh Kumar Dubey, Priyanka Singh, and R. K. Nagaria
IEEE
This paper presents an energy-efficient low-voltage double-tail dynamic latch comparator which shows high switching speed in comparison to conventional design. The proposed comparator is designed using improved pre-amplifier stage in which hybrid design style is adopted to enhance latch speed with optimum power. As a result, energy efficiency is improved. The analytical expressions for delay calculation are also derived for the proposed comparator. The rigorous simulations are analyzed in CADENCE SPECTRE at 90nm CMOS technology with 1V power supply. The mismatch analysis for offset voltage is validated using Monte-Carlo simulations at 200 samples. The simulations and analytical derivations corroborate that the enhanced speed is achieved with low-offset and optimized power dissipation. The simulation results confirm that the proposed design is about 2 times faster, 52.89% more energy efficient, and minimizes 27.51% offset voltage in contrast of conventional dynamic comparator at the cost of $20.39\\mu\\mathrm{W}$ power consumption and $54.03\\mu \\mathrm{m}^{2}$ active die area.
Avaneesh K. Dubey and R. K. Nagaria
Springer Science and Business Media LLC
This paper presents a low voltage double-tail dynamic comparator (DTDC) for fast and power-efficient data conversion. The amplification stage of the proposed DTDC is designed using self-biasing technique, which helps to reduce external biasing requirement to bias bulk/gate of the transistors. The self-biasing technique controls threshold voltage (Vth) of the transistors either for fast switching (low-Vth) or for low power dissipation (high-Vth). The latch stage of the proposed DTDC is designed with novel dynamic CMOS inverters to improve the regeneration speed. The mathematical equations for delay and offset voltage are derived for the proposed DTDC and improvements are mentioned. The proposed DTDC is designed in CADENCE and simulated with SPECTRE using 45 nm CMOS process technology at the low power supply of 0.8 V to verify the outcomes. The simulation results reveal that the delay and power dissipation of the proposed DTDC are 166.29 pS and 2.3 µW respectively. The analysis of 1-sigma offset error is performed using Monte-Carlo simulation. Here, the mismatch and process variation are considered and the samples are generated randomly till 200 samples (runs). Additionally, the peak input voltage error due to kickback noise is 0.219 mV for a differential input voltage of 5 mV.
Avaneesh K. Dubey and R. K. Nagaria
World Scientific Pub Co Pte Lt
This paper presents a novel high-speed and highly energy-efficient double-tail dynamic comparator. In order to achieve high speed, a hybrid design style is adopted for pre-amplifier stage and a new design is proposed for latch stage, which enhances the speed and reduces the effect of kickback noise. The latch stage delay and energy efficiency of the proposed design are optimized with respect to the width of each transistor. To verify the outcomes, the proposed comparator is simulated using 45[Formula: see text]nm and 180[Formula: see text]nm CMOS process. Monte Carlo simulation is also done for each parameter. The 45[Formula: see text]nm result shows that the comparator has the total delay as low as 104.3[Formula: see text]ps and consumes only 0.288[Formula: see text]fJ of energy per conversion from a 0.8[Formula: see text]V supply. The mean value of input voltage error due to kickback noise is found as 306[Formula: see text]nV.
Avaneesh K. Dubey, Pratosh K. Pal, Vikrant Varshney, Ankur Kumar, and R. K. Nagaria
IEEE
This paper addresses novel design of complementary metal oxide semiconductor (CMOS) Double tail dynamic comparators (DoTDCs) using offset control scheme. The offset control scheme adopted the phenomena of time-domain bulk-tuning to input transistors. The modification in offset control scheme and comparator core is done to reduce leakage through the bulk node and other issue noticed in design. The novel phase detector and charge pump are also proposed for high-speed, low power. Based on the proposed phase detector and charge pump, offset control scheme is designed, and using this two different DoTDCs, named as DoTDC-I and DoTDC-II are proposed. To verify the outcomes, they are simulated in SPECTRE at 0.8V of the supply voltage at 45nm CMOS technology node. Monte-Carlo simulation is done to obtain the offset voltage. The result shows that the offset-voltage is reduced from 1.608mV to 0.911mV in DoTDCI and from 1.694mV to 1.426mV in DoTDC-II structures using said control scheme.
Avaneesh K. Dubey and R. K. Nagaria
World Scientific Pub Co Pte Lt
A new design technique is proposed and discussed for the design of active load using the bulk-driven method. The proposed method uses gate-driven input drivers with bulk-driven MOS load. Further, it is used to design single stage amplifiers, such as common source (CS) and common gate (CG). In addition to the proposed technique, a very efficient method is implemented to improve and control the gain of the amplifiers, which is named as Gain Control by Bulk Amplification (GACOBA) Technique. The large signal, small signal and frequency domain analysis of proposed designs are done and to verify the outcomes it is simulated in SPECTER at 0.7[Formula: see text]V supply with 45[Formula: see text]nm CMOS technology. The result shows that the transconductance and gain of proposed single stage CS amplifier are increased without affecting impedance seen by output node. On the other hand, GACOBA technique is useful for gain enhancement in CS and CG amplifier.
Ankur Kumar, Vikrant Varshney, Pratosh Kumar Pal, R. K. Nagaria, and Avaneesh Kumar Dubey
IEEE
This paper presents a new wide fan-in domino OR-gate for high speed VLSI circuits with reduced power dissipation, lowered process variations and enhanced noise margin. In this work, some crucial modifications in evaluation network are done to increase the threshold voltage of PDN transistors in standby mode using stacking phenomenon hence reduction in the power dissipation of the proposed domino. Further, Noise immunity is also enhanced by overcoming the charge sharing problem. The idea used in this work is to effectively turn ON and OFF the keeper transistor so that overall power can be saved. The simulations are done under cadence virtuoso environment for wide fan-in (8, 16, 32 and 64-input) OR-gates using 45nm CMOS technology node at 1V power supply and 1GHz clock frequency respectively. The simulation results i.e. noise margin, average power, and standard deviation, show 29%, 21% and 32% improvements respectively in the proposed work as compared to standard domino gate.
Pratosh Kumar Pal, Avaneesh Kumar Dubey, Ankur Kumar, Vikrant Varshney, and Rajendra Kumar Nagaria
IEEE
This paper presents sub-1V, low voltage and low power reference voltage using a body biasing technique. The body biasing is used to generate a supply independent current as well as the output reference voltage. The gate to source voltage difference is used to obtain the output voltage. The proposed reference voltage is implemented and simulated in Cadence Virtuoso using SCL180nm CMOS technology model for 0.55-1.8V supply range. The average output reference voltage of 250mV is obtained at room temperature with the line regulation of 1.9mV/V. The supply current of 40nA is found at 0.55V supply along with minimum temperature coefficient (TC) of 28.6ppm/oC for a temperature range of -50 to 90oC. A high-value PSRR of - 44dB at 100Hz and -16dB at 1MHz is achieved. It has an area of 0.0036mm2.
Vikrant Varshney, Avaneesh K. Dubey, Ankur Kumar, Pratosh Kumar Pal, and R.K. Nagaria
IEEE
Dynamic comparators owing to low-power, low-offset, and high-speed beneficiate in several low-power analog/mixed-mode applications. In this paper, a double-tail dynamic latch comparator is intended which exhibits low-offset with optimized power having relatively comparable speed. In this paper, equation for delay is also derived for the proposed dynamic latch comparator. The mismatch analysis and meticulous simulations for the proposed comparator are carried out in CADENCE SPECTRE at 1V supply voltage and 90-nm CMOS technology. It confirms that the reduced offset voltage is achieved with optimized power which is validated by 0.2k Monte Carlo simulation process. The simulation outcomes corroborate that the proposed dynamic latch comparator is 32% more power saving, 30% energy efficient and exhibits 69% less offset voltage in comparison to conventional double-tail dynamic latch comparator having 13% less die area and comparable speed of 148.23pS.
Avaneesh K. Dubey and R.K. Nagaria
Elsevier BV
Abstract A novel approach is proposed and discussed for designing CMOS double-tail dynamic comparator using the bulk-driven method. The bulk-driven method proposed thus far for low-power circuits result in reduced transconductance. The proposed technique uses the gate driven method to drive the inputs with bulk-driven loads. For the proposed comparator, mathematical analysis of delay and offset due to mismatch is presented. Additionally, a new optimized architecture of control unit is proposed to control both, offset voltage and kickback noise. To verify the outcomes, it is simulated in SPECTRE at 0.8 V of the supply voltage at 45 nm CMOS technology node. The proposed comparator achieves over 87% reduction in latch delay and 27% reduction of energy consumption over a conventional design. Monte-Carlo simulation is done to obtain the offset voltage, the result shows that the offset voltage is reduced by 62% using optimization technique.
Rahul Jain, Avaneesh K. Dubey, Vikrant Varshney, and Rajendra K. Nagaria
IEEE
Regenerative comparators due to its power efficiency and high-speed finds usage in many high-speed and low-power analog-to-digital converters. In this paper, a novel comparator based on double-tail architecture is proposed to enhance latch regeneration speed. Upon analyzing the delay expressions of some existing double-tail structures, the structure of latch stage is modified by adding cross-coupled transistors to improve latch regeneration thus enhancing comparison speed. Mathematical expression for total delay is also calculated for the proposed comparator. The proposed comparator is designed in CADENCE and simulated in SPECTRE at 90-nm CMOS technology. The simulation results indicate that for the proposed comparator energy per conversion and total delay are reduced by more than 40% and 20% respectively as compared to conventional double-tail dynamic comparator.
Avaneesh K. Dubey, R. K. Nagaria, Pratosh K. Pal, and Rakesh K. Singh
IEEE
A constant-gm, rail-to-rail operational amplifier circuit topology is presented in this paper. The amplifier input stage is realized using single NMOS pair at 0.13μm bulk-CMOS process technology. The overall gain variation is within the range of ±2.338% for the rail-to-rail common mode input range. The proposed design is able to reject the common mode input response with 115dB of common mode rejection ratio (CMRR). High slew rate is achieved and the simulated value is +19/−43 (V/μs) of an unity gain buffer op-amp at 5pF of CL. The variation in overall gm and gain are also simulated at different corner temperatures. The circuit simulation is done in Tanner EDA at 1.8 V of power supply which dissipates the power of 6.1mW.
Pratosh Kumar Pal, Avaneesh Kumar Dubey, Sankit R. Kassa, and Rajendra Kumar Nagaria
IEEE
This paper presents design of wide fan-in gate for low power and high speed operations with reduced transistor count. In this work some circuital modifications are done to reduce the number of stacked transistor between input and output hence reducing the delay of the designed wide fan-in OR-gate. Also the average power dissipation of the circuit is reduced as it has less number of switching nodes. The idea used in this technique is the use of basic sense amplifier for comparing voltage generated at the two terminals of the logic block of designed circuit. This logic block represents 8, 16, 32 and 64-input OR-gate. The simulations are done for wide fan-in OR-gates using 90nm CMOS technology model with supply voltage of 1V at 110°C of temperature at clock frequency of 1GHz. The simulation results obtained is compared for 32-input OR-gate with standard voltage comparison based domino circuit for delay, average power and PDP which gives 2.5%, 6% and 9% improvements over it respectively.
Avaneesh Kumar Dubey, Pankaj Srivastava, and Manisha Pattanaik
IEEE
To draw an accurate relationship between power dissipation and speed is a challenging problem in operational Amplifier with switch capacitance. However, transformation of current steer circuit into charge steer is an efficient technique to reduce power dissipation even at higher speed. In this paper, an efficient model is proposed to estimate the 1st and 2nd stage operational Amplifier's power dissipation and delay, which can further used to design higher order Operational Amplifier, Voltage controlled Oscillator, Analog to Digital converters and other efficient power CMOS circuits. Analysis of 1st and 2nd stage Amplifier with BSIM4 model for CMOS in Tanner environment is done. The result shows that the power dissipation is reduced approximately 63% for 1st stage and 53:5% for 2nd stage Amplifier using charge steering technique at 90nm.