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MAHESH VAIDYA

RESEARCH ASSOCIATE-I · INDIAN INSTITUTE OF SCIENCE BENGALURU

https://researchid.co/mahesh91
@iisc.ac.in
17Scopus Publications
103Google Scholar Citations
6Google Scholar h-index
4Google Scholar i10-index

Research Interests

SEMICONDUCTOR DEVICES, VLSI

Biography

I am currently working as a postdoc research associate at IISc Bangalore, MSD’s Lab in the area of ESD effect on semiconductor devices. Previously, I have worked as an Assistant Professor in KL University, Hyderabad campus in the department of Electronics and Communication Engineering. I have completed Ph.D. under the guidance of Prof. Shrish Verma and Dr. Alok Naugarhiya from the National Institute of Technology Raipur. My area of research is Power Semiconductor Devices, more specifically worked on Insulated Gate Bipolar Transistor. During my research work I have published 4 articles in SCI journals including one in IEEE Electron Device Letters and one article in IEEE Transactions on Electron Devices. I have also worked as a Lab Engineer at National Institute of Technology Raipur under Special Manpower Development Program Chip to System Design (SMDP-C2SD) project. In this project, I have worked on Digital IC Design and have hands on experience in FPGA design.

Education

Ph.D. (ECE, National Institute of Technology Raipur) M.Tech. (VLSI System Technology, Shiv Nadar University) B.E. (CSVTU, Bhilai)

Recent Scopus Publications

  1. Proposal to Achieve the Ultimate Holding Voltage Tunability in Silicon Controlled Rectifiers (SCRs) for a Wide Range of ESD Protection Application
    IEEE International Reliability Physics Symposium Proceedings, 2025
  2. Novel Trigger Circuit & SCR Device Co-Engineering Based Local (I/O-VSS & I/O-VDD) ESD Clamp Concepts with Improved Latch-Up Susceptibility, Lower Leakage and Lower Capacitance for Ultra High Speed I/Os
    IEEE International Reliability Physics Symposium Proceedings, 2025
  3. Low Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High Speed Application
    Proceedings of the IEEE International Conference on VLSI Design, 2024
  4. Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR
    IEEE International Reliability Physics Symposium Proceedings, 2024
  5. Load-line Dependent Current Filament Dynamics in N anoscale SCR Devices
    IEEE International Reliability Physics Symposium Proceedings, 2024

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