Pavithra Guru R
Assistant Professor and Department of Computing Technology · SRM Institute of Science and Technology Kattankulathur
Research Interests
I am Dr. R. Pavithra Guru, Assistant Professor in the Department of CTech, SRMIST, with research expertise in VLSI Physical Design, intelligent optimization algorithms, ML-assisted EDA, and digital system design.
Biography
I am Dr. R. Pavithra Guru, Assistant Professor in the Department of CTech, SRMIST, with research expertise in VLSI Physical Design, intelligent optimization algorithms, ML-assisted EDA, and digital system design. My scholarly work includes multiple peer-reviewed publications, national patents, and ongoing research projects in circuit partitioning, CA-based optimization, and ML-driven semiconductor workflows. I regularly serve as a technical reviewer for conferences and journals in AI, VLSI, microelectronics, and embedded systems. With a strong academic foundation (B.E, M.E, PhD, PDF–UK), I am committed to advancing semiconductor research while fostering high-quality learning through project-based teaching, research mentorship, and industry-oriented curriculum development.
Education
Ph.D. in Information & Communication Engineering Anna University, Chennai 2017 – 2022 Research focus on VLSI design optimization and machine learning applications. M.E. in VLSI Design Anna University, Chennai 2014 – 2016 Graduated with first class honors. B.E. in Electronics and Communication Engineering Anna University, Chennai 2010 – 2014 Graduated with first class honors.
Recent Scopus Publications
- Optimized Auxiliary Classifier Wasserstein Generative Adversarial Network espoused Hypergraph Partitioning for VLSI Circuit Design
- ABO optimized hybrid Trans-CNN-Bi-GRU approach for intrusion detection in IoT networks: a privacy-preserving solution
- Cellular automata-based framework for yield optimization in VLSI physical design of large-scale benchmark circuits
- Real-Time Audio Pattern Detection for Enhancing Situational Awareness in Headphone Users Using Deep Learning
- Grey wolf optimization (GWO) based efficient partitioning algorithm VLSI circuits for reducing the interconnections
Research Outputs
Method for Improving the Performance of Very Large Scale Integration Patent Application No.: 202341049442A Date of Publication: 01 September 2023 4G and 5G Technology-Based Several-Antennas for Smartphone App Using Multimode Patent...
Links
- ORCID https://orcid.org/0000-0003-2403-1728
- Google Scholar https://scholar.google.com/citations?user=KulYAAAAJ&hl
- Scopus https://www.scopus.com/authid/detail.uri?authorId=57216546834
- Personal Weblink https://www.srmist.edu.in/faculty/dr-pavithra-guru/