Aditya S
Verified @gmail.com
Scopus Publications
- A Low cost area-efficient modified Russian peasant multiplier(MRPM) for biomedical applications
Guru Siva Subramanian V., Deepika Sree T.N., Aditya S.
Integration, 2025 - A Flexible Digitally Controlled Oscillator Structure to Reconfigure the Frequency Band in Multi-band RF AD-PLL System
S. Aditya, Sridharan Moorthi
IETE Journal of Research, 2023
Reconfigurable architectures are more prominent in modern-day multi-band radio systems. This work has been conceptualized for a flexible 8-bit digitally controlled oscillator (DCO) design to suit r... - Digitally tunable active inductor for RF-DCO applications
S. Aditya, S. Moorthi
International Journal of Electronics Letters, 2020
The design of a tunable differential active inductor by employing a digitally controlled current source is presented in this work. The design proposes a 4-bit digitally tunable active inductor (DTAI) suitable for multi-band radio frequency-digitally controlled oscillator (RF-DCO) applications. This DTAI has been implemented in standard 180 nm complementary metal–oxide–semiconductor (CMOS) process with a 1.8 V supply, and its performance is analysed. The post-layout simulation results show that DTAI emulates an inductance tuning range of 4 nH to 55 nH with self-resonant frequency ranging from 4.3 GHz to 14.6 GHz. The noise performance of the design along with its power consumption for digital codes [0001 to 1111] is plotted. The maximum quality factor ranges from 4 to 5 without the negative compensation resistor, maximum noise is 1.9 nV/ and maximum power dissipation is 10.5 mW. The layout of the proposed design is drawn, the total area occupied is 48.16 µm x 16.6 µm. An example implementation of the proposed 4-bit DTAI as a DCO targetting RF applications is discussed. - A wide tunable fast settling 4-bit digitally controlled oscillator for reconfigurable multi-band RF applications
Aditya S., Moorthi Sridharan
Microelectronics Journal, 2019
A digitally tunable differential active inductor based 4-bit digitally controlled oscillator to reduce the area and cost, for reconfigurable multi-band RF applications is proposed in this work. This design attains coarse frequency tuning of 0.571–3.74 GHz for digital control word {1 to 15} with percentage tuning range (%TR) of 147.02%. The noise analysis shows phase noise of −95.5 to −100.5 dBc/Hz @ 5 MHz offset with power consumption varying from 1.02 to 9.5 mW. The design achieves Figure-of-merit (FOM) of −146.07 dBc/Hz and Figure-of-merit with %TR (FOMT) of −169.416 dBc/Hz. The proposed design occupies an area of 44 μm × 18 μm in standard 180 nm CMOS technology. A thorough post layout analysis of the design including the parasitic RC components to test the DCO stability over process, voltage and temperature variations (PVT), has been carried out and the results are plotted. - A low jitter wide tuning range phase locked loop with low power consumption in 180nm CMOS technology
S. Aditya, S. Moorthi
Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, 2013
This paper describes a design of phase locked loop system suitable for clock synchronization and generation. PLLs with high speed, low noise and wide bandwidth with fast acquistion time are preferred. A PFD with low dead zone, charge pump with passive low pass filter and a low noise, wide tuning VCO are integrated in the PLL system. A novel current controlled oscillator(ICO) with wide tuning range of 420MHz to 3.1GHz and low phase noise of -66.83 dBc/Hz @ 1MHz offset is designed. The PFD modeled is a D-latch based digital PFD and conventional charge pump with second order loop filter is used. Integrating this ICO in a PLL system offers low jitter and wide bandwidth. This PLL system is simulated and tested in CADENCE UMC180nm technology. The results prove that the lock-in range of PLL is 500MHz to 1.5GHz with a maximum jitter of 27.1ps, maximum pull-in time is 420ns and the maximum power consumed by this PLL system is 343.7μW at 1.5GHz.
