Alpana Agarwal

Scopus Publications

Reference-free hybrid ANN based calibration for 12-bit sigma–delta modulator with dual-decimators
Nidhi Shukla, Anil Singh, Alpana Agarwal
AEU International Journal of Electronics and Communications, 2026
Unlocking the potential of the Na3SbSe4 based chalcogenide solar cell
Neelima Singh, Alpana Agarwal
Chemical Physics Letters, 2026
Voltage controlled ring oscillator with multi-frequency shift keying technique for jitter reduction in 180 nm CMOS technology
Abhishek Mishra, Anil Singh, Alpana Agarwal
Analog Integrated Circuits and Signal Processing, 2026
A low power SAR ADC with fine–tuned time based adaptive sampling technique for ECG monitoring application in 180 nm CMOS
Naveen Kandpal, Anil Singh, Alpana Agarwal
Integration, 2025
A Low Jitter and High-Speed Flash TDC with PVT Calibration and Its Testing Methodology
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
Lecture Notes in Electrical Engineering, 2025
A progressive phase multiple-injection locking technique for jitter suppression in voltage-controlled ring oscillator
Abhishek Mishra, Anil Singh, Alpana Agarwal
International Journal of Electronics, 2025
Computational investigation of lead-free NaZn0·7Ag0.3Br3 based double-perovskite solar cell
Neelima Singh, Alpana Agarwal, Mohit Agarwal
Journal of Physics and Chemistry of Solids, 2024
An artificial intelligence-based 4-to-10-bit variable resolution Flash ADC with 3.6 to 1.04 GS/s sampling rate
Naveen Kandpal, Anil Singh, Alpana Agarwal
International Journal of Circuit Theory and Applications, 2024
This paper presents an artificially intelligent Flash ADC with enhanced resolution from 4 to 10 bits. Unlike conventional approaches, this artificial intelligence (AI)‐based architecture avoids the use of many number of comparators in the Flash ADC when the ADC's resolution changes from 4 to 10 bits. This work initially gets the digital output of a 4‐bit existing Flash ADC as a training data set and then uses these 4‐bit output bits and sends to resolution enhancement logic (REL) block to vary its resolution without increasing the hardware complexities. After simulation, it is observed that the proposed ADC is of SNR of 24.13 dB for 4‐bit Flash ADC designed in SCL 180 nm CMOS technology and increases from 36.89 to 60.70 dB for 6 to 10‐bit resolution, respectively. The sampling frequency of the proposed architecture ranges from 3.6 to 1.04 GHz for a change in resolution from 4 to 10 bits. The FoM of 235 fJ/conv‐step in the training phase is obtained, and it varies from 56 to 20.3 fJ/conv‐step in the next phase of the testing and the prediction. The estimated area of the proposed 4‐to‐10‐bit variable resolution Flash ADC is μm2.
Numerical investigation of the Pb-free titanium-based double-perovskite solar cell
Neelima Singh, Alpana Agarwal, Mohit Agarwal
Journal of Nanoparticle Research, 2024
Voltage Controlled Ring Oscillator with Phase Compensation Technique for Jitter Reduction in 180 nm CMOS Technology∗
Abhishek Mishra, Anil Singh, Alpana Agarwal
Journal of Circuits Systems and Computers, 2024
This paper presents a novel jitter reduction technique for a voltage-controlled ring oscillator (VCRO). This technique is helpful in employing VCRO-based circuits like Analog to Digital Converter (ADC), Phase Locked Loop (PLL) and time-based circuits whose performance is severely degraded by high jitter. In the proposed technique, the jitter is extracted using Excess Phase Discrimination (EPD) block and is transformed into Pulse Width Modulated (PWM) signal, which is then fed into the Phase Compensator (PC) block. This block reduces the jitter by about half its value after enabling the Single Ended Injection Locking (SEIL). The proposed work is designed in SCL 180[Formula: see text]nm CMOS technology at 1.8 V supply. On enabling the proposed circuit, the Root Mean Square (RMS) jitter reduces from 5.94 to 2.58 ps (about 56%) for VCRO running at 58 MHz and consumes a total power of 375.84 [Formula: see text]W. The overall performance of the proposed circuit does not vary much in the post-layout simulations, hence demonstrating the effectiveness of the proposed technique.
Highly efficient lead-free ethyl ammonium substituted perovskite solar cell simulated using SCAPS 1D
Neelima Singh, Alpana Agarwal, Mohit Agarwal
Journal of Physics and Chemistry of Solids, 2024
An input signal dependent 8-to-12 bit variable resolution SAR ADC with digitally implemented bit enhancement Logic
Naveen Kandpal, Anil Singh, Alpana Agarwal
AEU International Journal of Electronics and Communications, 2023
Hybrid Voltage Compensation Topology based RF Rectifier for RF Energy Harvesting
Rajdevinder Kaur Sidhu, J. S. Ubhi, Alpana Agarwal, Balwinder Raj, Mandeep Singh
2023 2nd International Conference on Smart Technologies for Smart Nation Smarttechcon 2023, 2023
A Generalized Analytical Approach to Model the Gate Tunneling Current in Nanoscale Double Gate MOSFETs
Madhu Kushwaha, Arun Kumar Chatterjee, B. Prasad, A. K. Chatterjee, Alpana Agarwal
Silicon, 2022
A Transient-Enhanced Low-Power Standard-Cell-Based Digital LDO
Lalit Sood, Alpana Agarwal
Arabian Journal for Science and Engineering, 2022
A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
International Journal of Circuit Theory and Applications, 2022
A Machine Learning Driven PVT-Robust VCO with Enhanced Linearity Range
Naveen Kandpal, Anil Singh, Alpana Agarwal
Circuits Systems and Signal Processing, 2022
Functional validation of highly synthesizable voltage comparator on FPGA
Ashima Gupta, Anil Singh, Manu Bansal, Alpana Agarwal
Integration, 2022
A Scalable Fully-Digital Differential Analog Voltage Comparator
Ashima Gupta, Anil Singh, Alpana Agarwal
Journal of Circuits Systems and Computers, 2022
Study the effect of band offsets on the performance of lead-free double perovskite solar cell
Neelima Singh, Alpana Agarwal, Mohit Agarwal
Optical Materials, 2022
A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
Circuits Systems and Signal Processing, 2022
Intra and inter-patient arrhythmia classification using feature fusion with novel feature set based on fractional-order and fibonacci series
Amandeep Kaur, Sanjay Kumar, Ravinder Agarwal, Alpana Agarwal
Biomedical Signal Processing and Control, 2022
Authenticate IoT Data for Health Care Applications Using ATSHA204 and Raspberry Pi
Navneet Kaur Brar, Manu Bansal, Alpana Agarwal
Lecture Notes in Networks and Systems, 2022
RF Energy-based Smart Harvesting Systems
Emerging Technologies and Applications for A Smart and Sustainable World, 2022
Hardware Implementation of English to Regional Language Translator Using Arduino
Navneet Kaur Brar, Ajay Kumar, Manu Bansal, Alpana Agarwal
Lecture Notes in Networks and Systems, 2022
Performance of Copper Sulfide Hollow Rods in a Supercapacitor Based on Flexible Substrates
Ruby Garg, Alpana Agarwal, Mohit Agarwal
Journal of Electronic Materials, 2021
A CMOS standard-cell based fully-synthesizable low-dropout regulator for ultra-low power applications
Lalit Sood, Alpana Agarwal
AEU International Journal of Electronics and Communications, 2021
Bidirectional transfer learning model for sentiment analysis of natural language
Shivani Malhotra, Vinay Kumar, Alpana Agarwal
Journal of Ambient Intelligence and Humanized Computing, 2021
Effect of vanadium doping on MXene-based supercapacitor
R. Garg, A. Agarwal, M. Agarwal
Journal of Materials Science Materials in Electronics, 2021
A low-power high-resolution dynamic voltage comparator with input signal dependent power down technique
Ashima Gupta, Anil Singh, Alpana Agarwal
AEU International Journal of Electronics and Communications, 2021
Performance evaluation of lead–free double-perovskite solar cell
Neelima Singh, Alpana Agarwal, Mohit Agarwal
Optical Materials, 2021
Performance Improvement of Inorganic Lead-Free Perovskite Solar Cell
Neelima Singh, Alpana Agarwal, Mohit Agarwal
Communications in Computer and Information Science, 2021
A full input range, 1–1.8 V voltage supply scalable analog voltage comparator in 180nm CMOS
Ashima Gupta, Anil Singh, Alpana Agarwal
International Journal of Electronics, 2021
Numerical simulation of highly efficient lead-free perovskite layers for the application of all-perovskite multi-junction solar cell
Neelima Singh, Alpana Agarwal, Mohit Agarwal
Superlattices and Microstructures, 2021
Stand-alone Lightweight Security System for Native Language Using SPI Interface
Navneet Kaur Brar, Jaskaranbeer Kaur, Ajay Kumar, Manu Bansal, Alpana Agarwal
Lecture Notes in Networks and Systems, 2021
Computational analysis of cesium based inorganic perovskite solar cells using SCAPS-1D
Neelima Singh, Alpana Agarwal, Mohit Agarwal
Aip Conference Proceedings, 2020
Synthesis and characterization of solution processed MXene
Ruby Garg, Alpana Agarwal, Mohit Agarwal
Aip Conference Proceedings, 2020
Synthesis and optimisation of MXene for supercapacitor application
R. Garg, A. Agarwal, M. Agarwal
Journal of Materials Science Materials in Electronics, 2020
Numerical simulation of highly efficient lead-free all-perovskite tandem solar cell
Neelima Singh, Alpana Agarwal, Mohit Agarwal
Solar Energy, 2020
A fast locking and low jitter hybrid ADPLL architecture with bang bang PFD and PVT calibrated flash TDC
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
AEU International Journal of Electronics and Communications, 2020
A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μ m CMOS Technology
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
Journal of Circuits Systems and Computers, 2020
A 2.3 mW Multi-Frequency Clock Generator with - 137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
Journal of Circuits Systems and Computers, 2020
Numerical analysis of lead-free methyl ammonium tin halide perovskite solar cell
Neelima Singh, Alpana Agarwal, Mohit Agarwal
Aip Conference Proceedings, 2020
Implementation of Low Supply Rail-to-Rail Differential Voltage Comparator on Flexible Hardware for a Flash ADC
Ashima Gupta, Anil Singh, Alpana Agarwal
Journal of Circuits Systems and Computers, 2020
An Efficient R-Peak Detection Using Riesz Fractional-Order Digital Differentiator
Amandeep Kaur, Sanjay Kumar, Alpana Agarwal, Ravinder Agarwal
Circuits Systems and Signal Processing, 2020
Design and Analysis of Higher-Order Sigma Delta Modulator
Deepti Malhotra, Alpana Aggarwal
Advances in Intelligent Systems and Computing, 2020
A high resolution and low jitter 5-bit flash TDC architecture for high speed intelligent systems
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
Advances in Intelligent Systems and Computing, 2020
A Review on MXene for energy storage application: Effect of interlayer distance
Ruby Garg, Alpana Agarwal, Mohit Agarwal
Materials Research Express, 2020
A Novel Approach to ECG R-Peak Detection
Amandeep Kaur, Alpana Agarwal, Ravinder Agarwal, Sanjay Kumar
Arabian Journal for Science and Engineering, 2019
A Survey Study of Different RF Energy Sources for RF Energy Harvesting
Rajdevinder Kaur Sidhu, Jagpal Singh Ubhi, Alpana Aggarwal
2019 International Conference on Automation Computational and Technology Management Icactm 2019, 2019
Fast digital foreground gain error calibration for pipelined ADC
Jupinder Kaur, Prince Prabhakar, Anil Singh, Alpana Agarwal
Iet Circuits Devices and Systems, 2019
A novel thresholding technique for R-peak detection in ECG
Amandeep Kaur, Alpana Agarwal, Ravinder Agarwal, Sanjay Kumar
2019 2nd International Conference on Advanced Computational and Communication Paradigms Icaccp 2019, 2019
Highly-digital voltage scalable 4-bit flash ADC
Ashima Gupta, Anil Singh, Alpana Agarwal
Iet Circuits Devices and Systems, 2019
Software optimization of lightweight ciphers for resource constraint devices
Kiranjit Kaur, Manu Bansal, Alpana Agarwal, Ajay Kumar
Pdgc 2018 2018 5th International Conference on Parallel Distributed and Grid Computing, 2018
An efficient fully differential voltage comparator
Journal of Engineering Science and Technology, 2018
Low-power 10-bit 100 MS/s pipelined ADC in digital CMOS technology
Anil Singh, Veena Rawat, Alpana Agarwal
Iet Circuits Devices and Systems, 2017
A digital-based low-power fully differential comparator
Anil Singh, Ayushi Goel, Alpana Agarwal
Journal of Circuits Systems and Computers, 2017
Digital background calibration of charge pump based pipelined ADC
Anil Singh, Alpana Agarwal
International Journal of Electronics, 2016
Charge pump-based MOSFET-only 1.5-bit pipelined ADC stage in digital CMOS technology
Anil Singh, Alpana Agarwal
International Journal of Electronics, 2016
Research issues related to cryptography algorithms and key generation for smart grid: A survey
Ajay Kumar, Alpana Agarwal
India International Conference on Power Electronics Iicpe, 2016
Survey on authentication and encryption techniquesfor smart grid communication
Mansi Sharma, Alpana Agarwal
India International Conference on Power Electronics Iicpe, 2016
Genetic algorithm for ordering and reduction of BDDs for MIMO circuits
Manu Bansal, Alpana Agarwal
2013 3rd International Conference on Innovative Computing Technology Intech 2013, 2013
Ordering and reduction of BDDs for multi-input adders using evolutionary algorithm
Manu Bansal, Alpana Agarwal
Proceedings of the 2013 International Conference on Advanced Electronic Systems Icaes 2013, 2013
A Combined CMOS Reference Circuit with Supply and Temperature Compensation
Madhusoodan Agrawal, Alpana Agarwal
Communications in Computer and Information Science, 2013
Synthesis of analog IC building blocks
Alpana Agarwal, Chandra Shekhar
Proceedings 2011 IEEE Computer Society Annual Symposium on VLSI Isvlsi 2011, 2011
Figure-of-merit-based area-constrained design of differential amplifiers
Alpana Agarwal, Chandra Shekhar
VLSI Design, 2008
Carry circuitry for LUT-based FPGA
Proceedings of the IEEE International Conference on VLSI Design, 2004
Evolution of architectural concepts and design methods of microprocessors
Proceedings of the IEEE International Conference on VLSI Design, 1998
H∞ robust control technology applied to the design of a combined steering/stabilizer system for warships
Ship Control Systems Symposium Proceedings, 1997

Alpana Agarwal

RESEARCH INTERESTS

Scopus Publications