Alpana Agarwal

@thapar.edu

Professor and Head, Electronics and Communication Engineering
Thapar Institute of Engineering and Technology, Patiala, India



                 

https://researchid.co/alpana.agarwal

RESEARCH INTERESTS

VLSI Circuits and Systems, Mixed Signal Circuits, Smart Analog Circuits, Design-Synthesis of VLSI Circuits and Systems

64

Scopus Publications

Scopus Publications


  • A Low Jitter and High-Speed Flash TDC with PVT Calibration and Its Testing Methodology
    Jagdeep Kaur Sahani, Anil Singh, and Alpana Agarwal
    Springer Nature Singapore


  • An artificial intelligence-based 4-to-10-bit variable resolution Flash ADC with 3.6 to 1.04 GS/s sampling rate
    Naveen Kandpal, Anil Singh, and Alpana Agarwal
    Wiley
    AbstractThis paper presents an artificially intelligent Flash ADC with enhanced resolution from 4 to 10 bits. Unlike conventional approaches, this artificial intelligence (AI)‐based architecture avoids the use of many number of comparators in the Flash ADC when the ADC's resolution changes from 4 to 10 bits. This work initially gets the digital output of a 4‐bit existing Flash ADC as a training data set and then uses these 4‐bit output bits and sends to resolution enhancement logic (REL) block to vary its resolution without increasing the hardware complexities. After simulation, it is observed that the proposed ADC is of SNR of 24.13 dB for 4‐bit Flash ADC designed in SCL 180 nm CMOS technology and increases from 36.89 to 60.70 dB for 6 to 10‐bit resolution, respectively. The sampling frequency of the proposed architecture ranges from 3.6 to 1.04 GHz for a change in resolution from 4 to 10 bits. The FoM of 235 fJ/conv‐step in the training phase is obtained, and it varies from 56 to 20.3 fJ/conv‐step in the next phase of the testing and the prediction. The estimated area of the proposed 4‐to‐10‐bit variable resolution Flash ADC is  μm2.

  • Numerical investigation of the Pb-free titanium-based double-perovskite solar cell
    Neelima Singh, Alpana Agarwal, and Mohit Agarwal
    Springer Science and Business Media LLC

  • Voltage Controlled Ring Oscillator with Phase Compensation Technique for Jitter Reduction in 180 nm CMOS Technology
    Abhishek Mishra, Anil Singh, and Alpana Agarwal
    World Scientific Pub Co Pte Ltd
    This paper presents a novel jitter reduction technique for a voltage-controlled ring oscillator (VCRO). This technique is helpful in employing VCRO-based circuits like Analog to Digital Converter (ADC), Phase Locked Loop (PLL) and time-based circuits whose performance is severely degraded by high jitter. In the proposed technique, the jitter is extracted using Excess Phase Discrimination (EPD) block and is transformed into Pulse Width Modulated (PWM) signal, which is then fed into the Phase Compensator (PC) block. This block reduces the jitter by about half its value after enabling the Single Ended Injection Locking (SEIL). The proposed work is designed in SCL 180[Formula: see text]nm CMOS technology at 1.8 V supply. On enabling the proposed circuit, the Root Mean Square (RMS) jitter reduces from 5.94 to 2.58 ps (about 56%) for VCRO running at 58 MHz and consumes a total power of 375.84 [Formula: see text]W. The overall performance of the proposed circuit does not vary much in the post-layout simulations, hence demonstrating the effectiveness of the proposed technique.




  • Hybrid Voltage Compensation Topology based RF Rectifier for RF Energy Harvesting
    Rajdevinder Kaur Sidhu, J. S. Ubhi, Alpana Agarwal, Balwinder Raj, and Mandeep Singh
    IEEE
    In our contemporary context, the development of energy harvesting topology has drawn considerable interest. Due to its accessibility, RF energy harvesting is expected to have a promising future in producing a little amount of electrical power to operate a variety of low power electronics equipment. In order to transform an RF signal into usable electrical power, rectifier circuits with various compensation topologies are presented by different researchers. In this context, hybrid i.e. combination of Self Voltage Compensation and Internal Voltage Compensation is proposed to attain high efficacy than other existing topologies. The circuits are designed and simulated in Cadence Virtuoso Tool with 45nm CMOS technology. It is noted that the output voltage of 2.1V at 500MHz frequency.

  • A Generalized Analytical Approach to Model the Gate Tunneling Current in Nanoscale Double Gate MOSFETs
    Madhu Kushwaha, Arun Kumar Chatterjee, B. Prasad, A. K. Chatterjee, and Alpana Agarwal
    Springer Science and Business Media LLC

  • A Transient-Enhanced Low-Power Standard-Cell-Based Digital LDO
    Lalit Sood and Alpana Agarwal
    Springer Science and Business Media LLC

  • A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator
    Jagdeep Kaur Sahani, Anil Singh, and Alpana Agarwal
    Wiley
    AbstractA dual‐loop ADPLL architecture with 3‐bit flash TDC and background calibration‐based VCO is presented in this paper. The major aim of this work is to achieve the low jitter, low power, fast locking, and PVT‐insensitive ADPLL using simple flash TDC and gain calibrated VCO. A simple flash‐based 3‐bit TDC in the main loop is used which helps in achieving the fast locking with lower power consumption in ADPLL. The novel low phase noise VCO, with gain calibration in another loop, is used to fasten the locking process and jitter reduction due to any PVT variations. Therefore, both flash TDC and dual loop in the proposed ADPLL architecture help in achieving the fast locking. Proposed ADPLL is designed in SCL 180 nm CMOS technology at 1.8 V. The resolution of 3‐bit flash TDC is 3 ps. The achieved jitter of ADPLL is 1.83 ps with a phase noise of −153 dBc/Hz and locking time of 1.7 μs. Total power consumption is 5.3 mW at a frequency of 1.6 GHz.

  • A Machine Learning Driven PVT-Robust VCO with Enhanced Linearity Range
    Naveen Kandpal, Anil Singh, and Alpana Agarwal
    Springer Science and Business Media LLC

  • Functional validation of highly synthesizable voltage comparator on FPGA
    Ashima Gupta, Anil Singh, Manu Bansal, and Alpana Agarwal
    Elsevier BV

  • A Scalable Fully-Digital Differential Analog Voltage Comparator
    Ashima Gupta, Anil Singh, and Alpana Agarwal
    World Scientific Pub Co Pte Ltd
    This paper presents a scalable Fully-digital differential analog voltage comparator designed in Semi-Conductor Laboratory (SCL) 180[Formula: see text]nm complementary metal-oxide semiconductor technology. The proposed design is based on a digital design approach and is easily configurable to lower technology nodes. This design methodology makes the circuit less sensitive to process variations and takes fewer design efforts suitable for Systems-on-a-Chips (SOCs) application. The proposed circuit is designed and simulated in Cadence Virtuoso Analog Design Environment at the supply voltage ranging from 1[Formula: see text]V to 1.8[Formula: see text]V. The fully-digital analog voltage comparator has been synthesized using Synopsys Design Vision and auto-placed & auto-routed using Synopsys IC Compiler. This proposed comparator has a resolution of up to 7-bit at a supply voltage of 1.8[Formula: see text]V and a worst-case operating frequency of about 750 MHz at the TT corner. The obtained value of the offset voltage and delay is 0.55[Formula: see text]mV and 0.72 ns, respectively. The simulated results have shown that the power dissipation of the proposed scalable analog voltage comparator is [Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V supply voltage, respectively. Also, the RC extracted post-layout simulations have been implemented to verify the performance, which does not affect the results much.


  • A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS
    Jagdeep Kaur Sahani, Anil Singh, and Alpana Agarwal
    Springer Science and Business Media LLC


  • RF Energy-based Smart Harvesting Systems


  • Authenticate IoT Data for Health Care Applications Using ATSHA204 and Raspberry Pi
    Navneet Kaur Brar, Manu Bansal, and Alpana Agarwal
    Springer International Publishing

  • Hardware Implementation of English to Regional Language Translator Using Arduino
    Navneet Kaur Brar, Ajay Kumar, Manu Bansal, and Alpana Agarwal
    Springer Singapore

  • Performance of Copper Sulfide Hollow Rods in a Supercapacitor Based on Flexible Substrates
    Ruby Garg, Alpana Agarwal, and Mohit Agarwal
    Springer Science and Business Media LLC
    High electrical conductivity and superior redox properties of metal sulfide-based supercapacitors have attracted much attention in recent years. The simple and cost-effective method in the fabrication of high-performance supercapacitors is currently in high demand. In this paper, low-cost one-dimensional copper sulfide (Cu2S) electrodes are synthesized on glass as well as on flexible substrates such as polyethylene terephthalate (PET) and polypropylene (PP). The effect of the deposition quantity of Cu2S-1:1 on the glass substrate is also discussed. The synthesis of copper sulfide was done at room temperature by reducing copper sulphate pentahydrate using ascorbic acid as a reducing agent in sodium thiosulphate with 2 h of total reaction time. Scanning electron microscopy and x-ray diffraction characterizations are performed to validate the formation of Cu2S hollow rods. Electrochemical measurements such as cyclic voltammetry, galvanostatic charge-discharge, and electrochemical impedance spectroscopy are performed using a Metrohm Autolab workstation. Cyclic voltammetry is performed to measure the capacitance of Cu2S-based supercapacitors in which the ratio of copper sulphate and sodium thiosulphate was varied from 1:0.5 to 1:1.5 with a step size of 0.5, and the deposition quantity of Cu2S-1:1 film was also varied on glass substrate from 1 mg to 2 mg. The results show that the device with a 1:1 ratio shows the highest capacitance, i.e., 587 mF/cm2 as compared to the devices fabricated with a 1:0.5 ratio, 1:1.5 ratio, and 1:1 ratio with greater deposition. This is mainly because the 1:1 ratio has less resistance and has a hollow rod structure which allows the electrolyte ions to penetrate in Cu2S active material and thus, facilitates fast electron transport resulting in high-performance supercapacitors. Further, to understand the increased capacitive properties of a copper sulfide-based supercapacitor, processes involving charge transfer and mass transport are investigated by performing electrochemical impedance spectroscopy (EIS). The radius on the EIS plot of Cu2S-1:1 is smaller as compared to the other three samples on the glass substrate. Also, the resistance of Cu2S-1:1 with greater deposition is more than the Cu2S-1:1 sample because the increased amount of electrode material leads to increased paths for the electrolyte ions to interact with the electrode material. Further, this paper also discusses the successful fabrication of the supercapacitor devices on flexible PP substrate using 1-D Cu2S for the first time. The results show that the capacitance value on the flexible substrate is on par with that of glass substrates. Also, the synthesized copper sulfide 1:1 sample exhibits excellent stability with the capacitance retention of 85.7%, 91.1%, 86.18%, and 92.8%, respectively, on PP, glass, PET, and Cu2S-1:1 with more deposition on glass substrate after 3500 cycles.


  • Bidirectional transfer learning model for sentiment analysis of natural language
    Shivani Malhotra, Vinay Kumar, and Alpana Agarwal
    Springer Science and Business Media LLC