Performance Enhancement of Unconventional Slotted Waveguide Antenna Arrays at Ku Band A. S. Keerthi Nayani, G. Manmadha Rao International Journal of Communication Systems, 2025 Slotted waveguide antenna (SWA) arrays are highly valued for their compact structure, high power handling capability, directivity, and efficiency, making them ideal for advanced radar and communication systems. In broad‐wall SWAs, side lobe levels (SLLs) are influenced by slot displacement from the waveguide centerline and slot inclination angles, impacting array performance. This paper introduces a novel design approach for meandered SWA arrays optimized as frequency scanning antennas (FSAs), achieving enhanced gain, scanning coverage, and SLL suppression. The design incorporates an innovative meandering feeding mechanism, significantly improving frequency scanning performance over the Ku band (15.1–16.5 GHz). The array includes 16 radiating slot elements paired with an E‐plane horn antenna in elevation plane, narrowing beam width, and optimizing radiation control. Using the discrete Taylor distribution to meet SLL requirements, this approach effectively balances low SLL with high gain. Simulations conducted in CST Microwave Studio confirm the array's performance, showing 70° scanning coverage, over 21 dBi gain, and an SLL reduced to −21 dB. Both simulated and measured results designate that the proposed meandered SWA array architecture is appropriate for next‐generation frequency scanning systems, offering a compact, power‐efficient, and high‐precision solution for demanding applications.
Virtual Healthcare with AI 16th International Conference on Advances in Computing Control and Telecommunication Technologies Act 2025, 2025
VLSI Implementation of Blanking Cover Pulse and CBCP module Propagation for External System Interface Ranga Anurag, A S Keerthi Nayani 2023 International Conference for Advancement in Technology Iconat 2023, 2023 External system is a subsystem which is a part of a receiver application. The Composite Blanking Cover Pulse module (CBCP) is one of the major functional modules which need to be designed & developed for the External Sub-system. The external system (target hardware) is designed and developed based on Virtex 5 FPGA. The function of Composite Blanking Cover Pulse Module is that it will receive Input Trigger Pulse from various subsystems in different frequency bands on pulse-pulse basis and in turn generates respective blanking cover pulses for all the input trigger pulses. Subsequently, using these individual blanking cover pulses, a final composite cover pulse using various time parameters need to be generated on a pulse-topulse basis. The composite blanking cover pulse module uses various pulse parameters and various timing parameters for generation of composite blanking cover pulse. This CBCP is very essential to safeguard the main ESM system. The Master clock is used in 40 MHz All the intermediate control/signals should be synchronous with respect to master clock. The entire firmware must be developed using VHDL language. Finally, all the developed code is tested for its complete functionality in the simulated environment using Xilinx ISE (14.7) software [6].
Implementation of Virual Instrumentation for Signal Acquisition and Processing Devendra Singh, A S Keerthi Nayani, M. Sundar Rajan, Ranjeet Yadav, Joel Alanya-Beltran, et al. Proceedings of the 2022 International Conference on Innovative Computing Intelligent Communication and Smart Electrical Systems Icses 2022, 2022 National Instruments collaborated on virtual instruments. The programme for instruments, "LabVIEW," allows users to have sophisticated equipment within the software while performing measurements in a laboratory or in the field. Engineers and researchers can even create their own instruments utilising software-simulated signals using virtual instruments. The development and application of programmable measuring systems has received a lot of attention. The ability to change the measurement technique simply by altering the algorithm implemented by the computer-based architecture without having to replace the hardware components simplifies the experiment. By using a visual interface, virtual measurement systems have been proposed to make the design, implementation, and usage of programmable measuring systems easier. Data Acquisition.
Design of 16-Bit and 32-Bit Approximate Full Adder Using Majority Logic Poojitha Lagidi, Aenugula Iswarya, Gangarapu Rajesh, A.S. Keerthi Nayani 2021 2nd Global Conference for Advancement in Technology Gcat 2021, 2021 With the increasing technology rises the need of increase in storage. An adder is best known for performing arithmetic operations that takes n-input and produces two outputs i.e., sum and carry out. This paper proposes a 16-bit and 32-bit Approximate Full Adder based on Majority Logic. Use of approximate computing increases the storage capacity. The Majority Logic has become a basic gate for most of advanced circuits. We are using a majority logic that is composed with simple AND gates. Hence, with the use of Majority Logic and approximate computing, the delay and area consumed by the components can be reduced. The proposed Adder is designed with the one-bit approximate full adder based on the majority logic. A commendable reduce in delay by 77% and 82% is obtained for 16-bit and 32-bit design respectively and utilized area by the components is decreased by 54.8% and 51.5% for 16-bit and 32-bit design respectively when compared to existing designs.
Implementation of audio codec with a novel design methodology Dr. R. Prkash rao*, Mrs. A. S. Keerthi Nayani, Mrs. K. Aruna, Mr. A. Abhishek Reddy, and International Journal of Innovative Technology and Exploring Engineering, 2019 Currently in the real-time audio applications fixed point CODEC is being used. But the major disadvantage of such CODEC is the speed and accuracy. Because , as the DSP systems cannot be operated with real-time signal ‘t’, but they can be operated with the discrete time ‘n’ , the real-time analog signal x(t) is to be converted into discrete time signal x(n) by the analog to digital convert (ADC). The most widely used ADC in the signal processing environment is sigma-delta ADC. But, it can operate with the maximum speed of 1MHz. The DSP processor can give several times more speed than sigma-delta ADC. Hence, the speed of DSP system is being limited by sigma-delta ADC, even though the DSP system has the capability to operate with great speed. Similarly, the accuracy is being missed because the floating point samples are converted into fixed point to get the compatibility with fixed point DSP processor. To eliminate these two bottlenecks the novel design methodology has been proposed in which the ADC and DAC have been eliminated and the system is developed by the 16 bit floating point.
Design and implementation of uart protocol for avionics applications A. S. Keerthi Nayani, G. Nikhilesh, S. Shiva Tej Kumar 2019 International Conference on Intelligent Computing and Control Systems Iccs 2019, 2019 Revolutionary strides that serial communication has made in the past four decades, importance of serial communication has been realized and in today’s world these serial communication ports are included in even high-end FPGA’s. UART is a serial communication protocol which is used as a transmitter and receiver to transmit and receive data asynchronously via UART ports present in FPGA’s. UART converts parallel data to serial for transmitting the data and serial data to parallel for receiving the data. For fast transmission of information UART uses Buffer and can also be up to 2 kilo bytes. It has extra registers to provide information about transmission states and flow of data from ports and to govern the plethora of data when accepting device is not prepared to accept the information. UART can glide the data when it has a huge buffer to hoard the data coming from the transmitter and receiver. The size of the buffer is contingent with the design of the UART. This Universal Asynchronous Receiver Transmitter protocols are implemented in Remote data acquisition units (RDAU) present in missiles as a part of telemetry which is an avionics application. KEYWORDS: RDAU, Transmitter, Receiver, Verilog HDL, Vivado 2018.3, FPGA
RECENT SCHOLAR PUBLICATIONS
Performance Enhancement of Unconventional Slotted Waveguide Antenna Arrays at Ku Band AS Keerthi Nayani, G Manmadha Rao International Journal of Communication Systems 38 (3), e6114 , 2025 2025.0 Citations: 1
Virtual Healthcare with AI. BV Ramana, AS Nayani, R Sandhya, C Sekhar, NLV Venugopal Grenze International Journal of Engineering & Technology (GIJET) 11 , 2025 2025.0
Slotted meandered waveguide antenna for X-band radar applications AS Keerthi Nayani, G Manmadha Rao International Journal of Electronics 112 (7), 1249-1270 , 2024 2024.0 Citations: 2
LTE and MMW 5G Integrated MIMO Antenna System CAS ASK Nayani INDIAN JOURNAL OF SCIENCE AND TECHNOLOGY 17 (2), 301-311 , 2024 2024.0 Citations: 1
VLSI Implementation of Blanking Cover Pulse and CBCP module Propagation for External System Interface R Anurag, ASK Nayani 2023 International Conference for Advancement in Technology (ICONAT), 1-6 , 2023 2023.0
Lung Cancer Recognition Using CT Scan with CNN-VGG19 and PNN MMN Mrs A S Keerthi Nayani, Mrs. G.Swapnasri NeuroQuantology,eISSN 1303-5150 20 (Issue 10), 2654-2662 , 2022 2022.0
Implementation of virual instrumentation for signal acquisition and processing D Singh, ASK Nayani, MS Rajan, R Yadav, J Alanya-Beltran, ... 2022 International Conference on Innovative Computing, Intelligent … , 2022 2022.0 Citations: 8
Design of 16-Bit and 32-Bit Approximate Full Adder Using Majority Logic P Lagidi, A Iswarya, G Rajesh, ASK Nayani 2021 2nd Global Conference for Advancement in Technology (GCAT) , 2021 2021.0 Citations: 16
Emotion recognition through human conversation using machine learning techniques C Sekhar, MS Rao, ASK Nayani, D Bhattacharyya Machine Intelligence and Soft Computing: Proceedings Of ICMISC 2020, 113-122 , 2021 2021.0 Citations: 20
Enhancing image resolution and denoising using autoencoder AS Keerthi Nayani, C Sekhar, M Srinivasa Rao, K Venkata Rao Data Analytics and Management: Proceedings of ICDAM, 649-659 , 2021 2021.0 Citations: 10
Low-Power CMOS 1-Bit Full Adder using FPGA KIT & DSM Technology D Lakshmaiahe Turkish Journal of Computer and Mathematics Education Vol 12 (3), 5720-5725 , 2021 2021.0
Design and Implementation of Uart Protocol for Avionics Applications ASK Nayani, G Nikhilesh, SST Kumar 2019 International Conference on Intelligent Computing and Control Systems … , 2019 2019.0 Citations: 6
Implementation of Novel Floating Point Adder for High Speed DSP Applications KP Dr. R. Prakash Rao , B. Indira Priyadarshini , N.A.S. Keerthi Jour of Adv Research in Dynamical & Control Systems 11 (Special Issue-08 … , 2019 2019.0
Implementation of Audio CODEC with a Novel Design Methodology AAR R. Prakash Rao, A. S. Keerthi Nayani, Aruna Kokkula International Journal of Innovative Technology and Exploring Engineering … , 2019 2019.0
Effective food grain loss reduction technique using IOT CHSAK A S Keerthi Nayani International Journal of Creative Research Thoughts (IJCRT-2018), 45-49 , 2018 2018.0
Power-Efficient Carry Select Adder ASK Nayani, A Kokkula 2017.0
Performance Comparison of Weighted Modulo (2n +1) Adder using Different Prefix Structures ASKNA Kokkula 6th International Conference on Research Trends in Engineering, Applied … , 2017 2017.0
Performance comparison of weighted modulo (2n+1) adder using different prefix structures ASKNA KOKKULA International Journal of Electronics, Electrical and Computational System … , 2017 2017.0
VLSI ARCHITECTURE FOR PARALLEL MULTIPLIERS ASK NAYANI, A KOKKULA International Journal of Creative Research Thoughts (IJCRT) 4 (MAY 2017) , 2017 2017.0
Implementation of Audio CODEC with a Novel Design Methodology RP Rao, ASK Nayani, A Kokkula, AA Reddy
MOST CITED SCHOLAR PUBLICATIONS
Emotion recognition through human conversation using machine learning techniques C Sekhar, MS Rao, ASK Nayani, D Bhattacharyya Machine Intelligence and Soft Computing: Proceedings Of ICMISC 2020, 113-122 , 2021 2021.0 Citations: 20
Design of 16-Bit and 32-Bit Approximate Full Adder Using Majority Logic P Lagidi, A Iswarya, G Rajesh, ASK Nayani 2021 2nd Global Conference for Advancement in Technology (GCAT) , 2021 2021.0 Citations: 16
Enhancing image resolution and denoising using autoencoder AS Keerthi Nayani, C Sekhar, M Srinivasa Rao, K Venkata Rao Data Analytics and Management: Proceedings of ICDAM, 649-659 , 2021 2021.0 Citations: 10
Implementation of virual instrumentation for signal acquisition and processing D Singh, ASK Nayani, MS Rajan, R Yadav, J Alanya-Beltran, ... 2022 International Conference on Innovative Computing, Intelligent … , 2022 2022.0 Citations: 8
Design and Implementation of Uart Protocol for Avionics Applications ASK Nayani, G Nikhilesh, SST Kumar 2019 International Conference on Intelligent Computing and Control Systems … , 2019 2019.0 Citations: 6
Slotted meandered waveguide antenna for X-band radar applications AS Keerthi Nayani, G Manmadha Rao International Journal of Electronics 112 (7), 1249-1270 , 2024 2024.0 Citations: 2
Performance Enhancement of Unconventional Slotted Waveguide Antenna Arrays at Ku Band AS Keerthi Nayani, G Manmadha Rao International Journal of Communication Systems 38 (3), e6114 , 2025 2025.0 Citations: 1
LTE and MMW 5G Integrated MIMO Antenna System CAS ASK Nayani INDIAN JOURNAL OF SCIENCE AND TECHNOLOGY 17 (2), 301-311 , 2024 2024.0 Citations: 1
Virtual Healthcare with AI. BV Ramana, AS Nayani, R Sandhya, C Sekhar, NLV Venugopal Grenze International Journal of Engineering & Technology (GIJET) 11 , 2025 2025.0
VLSI Implementation of Blanking Cover Pulse and CBCP module Propagation for External System Interface R Anurag, ASK Nayani 2023 International Conference for Advancement in Technology (ICONAT), 1-6 , 2023 2023.0
Lung Cancer Recognition Using CT Scan with CNN-VGG19 and PNN MMN Mrs A S Keerthi Nayani, Mrs. G.Swapnasri NeuroQuantology,eISSN 1303-5150 20 (Issue 10), 2654-2662 , 2022 2022.0
Low-Power CMOS 1-Bit Full Adder using FPGA KIT & DSM Technology D Lakshmaiahe Turkish Journal of Computer and Mathematics Education Vol 12 (3), 5720-5725 , 2021 2021.0
Implementation of Novel Floating Point Adder for High Speed DSP Applications KP Dr. R. Prakash Rao , B. Indira Priyadarshini , N.A.S. Keerthi Jour of Adv Research in Dynamical & Control Systems 11 (Special Issue-08 … , 2019 2019.0
Implementation of Audio CODEC with a Novel Design Methodology AAR R. Prakash Rao, A. S. Keerthi Nayani, Aruna Kokkula International Journal of Innovative Technology and Exploring Engineering … , 2019 2019.0
Effective food grain loss reduction technique using IOT CHSAK A S Keerthi Nayani International Journal of Creative Research Thoughts (IJCRT-2018), 45-49 , 2018 2018.0
Power-Efficient Carry Select Adder ASK Nayani, A Kokkula 2017.0
Performance Comparison of Weighted Modulo (2n +1) Adder using Different Prefix Structures ASKNA Kokkula 6th International Conference on Research Trends in Engineering, Applied … , 2017 2017.0
Performance comparison of weighted modulo (2n+1) adder using different prefix structures ASKNA KOKKULA International Journal of Electronics, Electrical and Computational System … , 2017 2017.0
VLSI ARCHITECTURE FOR PARALLEL MULTIPLIERS ASK NAYANI, A KOKKULA International Journal of Creative Research Thoughts (IJCRT) 4 (MAY 2017) , 2017 2017.0
Implementation of Audio CODEC with a Novel Design Methodology RP Rao, ASK Nayani, A Kokkula, AA Reddy
