Dhanesh M S

@rajagiritech.edu.in

Assistant Professor Department of Electronics & Communication
Rajagiri School of Engineering & Technology



                 

https://researchid.co/dhaneshms

EDUCATION

M. Tech in VLSI & Embedded Systems
B.Tech in Electronics & Communication

2

Scopus Publications

8

Scholar Citations

2

Scholar h-index

Scopus Publications

  • A body biased adiabatic dynamic differential logic(BADDL) to prevent DPA attacks in smart cards
    P. Elana Andrews and M. S. Dhanesh
    IEEE
    Credit cards, access cards become a part of our daily life. So it becomes a serious issue to provide a secured integrated chips. Software security at algorithmic level is provided by using triple Data Encryption Standard(DES). But security at hardware level is still a question. Side channel attacks are the common type under the hardware attack. Side channel attacks can reveal secret key through leaked secondary information. Differential power analysis(DPA) attacks are the strongest side channel attack. DPA attacks are discussed in this paper. These attacks are based on relating the power consumption of the circuit and its input. DPA attacks discloses the secret key by connecting the power consumption and switching activity. To make power consumption independent of switching activity, This paper presents a new logic called body biased adiabatic dynamic differential logic(BADDL) to avoid DPA attacks in the smart cards. A voltage of 0.25V is applied for forward body biasing. For this logic, all logical operations have a constant power consumption which avoid the attacker to identify logical operation, So this prevents revealing the secret key. The benefits of this logic is illustrated by comparing the average power of BADDL with another ADDL logic called Performance adiabatic dynamic differential logic(PADDL) and also with CMOS logic. It is done in Cadence virtuoso at 45nm Technology.

  • Design of graphics processing unit for image processing
    J. George Cherian Panappally and M. S. Dhanesh
    IEEE
    This work describes the designing of a Graphics Processing unit that deals with image processing. Graphics Processing Unit (GPU) is an important factor when it comes to large computing. Images and videos that are having large data can be processed efficiently in GPU by exploiting its feature of parallel execution. Digital image processing implemented on hardware provides higher processing speed and performance. The use of Verilog HDL for the design of GPU provides an immediate implementation possibility. The paper focuses on image processing operations like Brightness manipulation, Contrast manipulation, image cropping, image zooming, image rotation and morphological operators such as Dilation and Erosion.

RECENT SCHOLAR PUBLICATIONS

  • A Comparative Study on the Diagnosis of Skin Cancer using different Models in Deep Learning
    DMS Surya S Kumar
    International Journal of Science and Research (IJSR) 9 (Issue 6, June 2020 2020

  • Indoor Localization based on Ultra Wide Band using Deca-Wave
    G Raj, VP Roy, MS Dhanesh
     2020

  • A body biased adiabatic dynamic differential logic (BADDL) to prevent DPA attacks in smart cards
    PE Andrews, MS Dhanesh
    2017 International Conference on Intelligent Computing and Control Systems 2017

  • Design of graphics processing unit for image processing
    JGC Panappally, MS Dhanesh
    2014 First International Conference on Computational Systems and 2014

  • An Efficient Way to Implement Scalar Multiplication In Elliptic-Curve Cryptography
    SK Sunny, MS Dhanesh

MOST CITED SCHOLAR PUBLICATIONS

  • A body biased adiabatic dynamic differential logic (BADDL) to prevent DPA attacks in smart cards
    PE Andrews, MS Dhanesh
    2017 International Conference on Intelligent Computing and Control Systems 2017
    Citations: 5

  • Design of graphics processing unit for image processing
    JGC Panappally, MS Dhanesh
    2014 First International Conference on Computational Systems and 2014
    Citations: 3