Firas N. Agha Received B.Sc. in Medical Instruments Engineering from Mosul Technical College and M.Sc. in Electronics and Communications Engineering from University of Mosul, Iraq, in 1998 and 2013 respectively. He completed his Ph.D. 2026 in the field of Nano electronics from the Department of Electrical Engineering, College of Engineering, Mosul University, Iraq. His research interests include Microelectronics, Nano Technology, TFET and NSFET.
RESEARCH, TEACHING, or OTHER INTERESTS
Electrical and Electronic Engineering, Engineering
11
Scopus Publications
79
Scholar Citations
6
Scholar h-index
5
Scholar i10-index
Scopus Publications
Evaluation and Optimization of Novel Graphene Nanosheet FET: Analog/RF Perspectives , Firas Natheer Abdul-Kadir Agha, Khalid Khaleel Mohammad, , Hussein Ali Al Abdulqader, , Billel Smaani, and International Journal of Electrical and Electronic Engineering and Telecommunications, 2026 Graphene Nano-Sheet Field Effect Transistor (GNSFET) is designed using a new material (graphene) in the channel, marking advancement in Nano-Sheet Field Effect Transistor (NSFET) technology. The device’s analog/Radio Frequency (RF) performance are evaluated with respect to the main geometric parameters of GNSFET, such as the gate-length, the channel-width, and the channel- thickness. Key analog/RF performance metrics, including the following: ION/IOFF ratio, subthreshold-swing SS, transconductance gm, transconductance efficiency gm/Id, output conductance gds, gate capacitance Cgg, cut-off frequency FT, and intrinsic gain Av. Output results reveal that scaling-down Tch to 6 nm, Wch to 14 nm, and Lg to 16 nm enhances the ION/IOFF ratio to 5.2×1011 and reduces SS to 60.05 mV/dec, which creates better switching efficiency. Reducing Tch from 8 nm to 6 nm, and Wch from 18 nm to 12 nm boosts the ION/IOFF ratio by 34.48% and 33.19%, respectively, highlighting the main role of device’s small geometry in improving electrostatic control. Transconductance gm increases by 22.51% when Lg is scaled from 16 nm to 12 nm, while Cgg decreases with reductions in Lg, Wch, and Tch, aligning with graphene’s inherent high carrier mobility. Notably, FT improves by 11.71% under Tch scaling, underscoring graphene’s potential for high-frequency RF applications. Although, intrinsic-gain (Av) benefits from Wch and Tch scaling, it exhibits a significant augmentation of 38.88% when Lg is increased from 12 nm to 16 nm, reflecting a trade-off between gain optimization and speed.
REVIEW ON PERFORMANCE PERSPECTIVES OF DIELECTRIC MATERIALS USED IN ADVANCED SEMICONDUCTOR DEVICES FOR VARIOUS APPLICATIONS Firas Natheer Agha, Faris Hassan Taha, Billel Smaani, Nawfal Y. Jamil, Nawaz Shafi Kufa Journal of Engineering, 2026 Dielectric materials are important for use in micro- and nanoelectronics systems, as well as in devices like Thin Film Transistors (TFT), planar waveguides, solar elements, and Light Emitted Diode (LED). The synthesis of such materials, alongside the acquisition of physical information. On their structural, optical, and electronic properties, is very important for the development of new stable devices based on them. The new special issue of “Materials” will include research articles and review papers written by leading scholars in field of materials science and technology. Actually, dielectrics have the thin layer created have good insulating qualities and an effective dielectric constant. Adapted single, binary, and perovskite oxides can be manufactured to provide dielectric materials with high dielectric constant. The benefits of using nanomaterial of using nanomaterial structures in energy storage devices with distinct performance are reviewed and discussed. The advancements in dielectric materials derived from a thin-materials methodology are assessed
Influence of Temperature on Nanosheet FET Performances Firas Natheer Abdulkadir Agha, Khalid Mohammed, Hussein Ali AL Abdulqader, Billel Smaani Ece 2025 2025 2nd International Conference on Electronic and Computer Engineering, 2025 Nanosheet Field Effect Transistor (NSFET) is constructed through the use of Technology Computer-Aided Design (TCAD), marking advancement in nanosheet FET technology. The device's performance are evaluated with respect to the influence of temperature of NSFET <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(T=225 ~\mathrm{K}, 275 \mathrm{K}, 325 ~\mathrm{K}$</tex> and 375 K). Geometrical dimensions for NSFET are adopted as follows: length of gate <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\left(L_{g}\right)=12 ~\text{nm}$</tex>, width of channel <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\left(W_{c h}\right)=14 ~\text{nm}$</tex> and thickness of channel <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\left(T_{c h}\right)=8 ~\text{nm}$</tex>. Key performance metrics have been analyzed targeting the optimization process, including: transconductance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\left(g_{m}\right)$</tex>, transconductance efficiency <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(g_{m} / I_{d})$</tex>, output conductance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(g_{d s})$</tex>, gate capacitance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\boldsymbol{C}_{g g})$</tex>, cut-off frequency <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\boldsymbol{F}_{T})$</tex>, intrinsic gain (AV), gain frequency product (GFP), transcounductance frequency product (TFP), gain transcounductance frequency product (GTFP). As temperature decreases, output results reveal that <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\left(F_{T}\right)$</tex> improves by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$21.23 \%,\left(g_{m}\right)$</tex> by 40.6%, and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\left(A_{V}\right)$</tex> by 46.6%. While temperature decrease, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(C_{g g})$</tex> decrease by 11.42%.
Down scaling Impact on The ION/IOFF Ratio of Nanosheet FET Digital Applications Firas Natheer Agha, Khalid Khalel Mohammed, Hussain Al Abdulqader, Billel Smaani 2025 15th International Conference on Electrical Engineering Iceeng 2025, 2025 The Nanosheet Field Effect Transistor (NSFET) device is designed by using graphene material in channel. Then used Silvaco Tools to simulate it. It might be considered an outstanding design of nanosheet FET device. The optimization method has taken into account several types of parameters, including the following: Drive current (ION), off current (IOFF), Sub-threshold Swing. (SS) and ION/IOFF. ratio. The impacts of varying device dimensions for GNSFETs are investigated and optimized. The dimensions of the gate length (Lg = 12,14, and16) nm, width of gate (Wg = 12,14,16 and 18) nm, and height of gate (Hg = 6,7 and 8) nm. The results showed that the ION/IOFF ratio is enhancement to 5.2×1011 and (SS) is enhanced performance to 60.05 mV/decade at Lg=16 nm, Wg=14nm and Hg=6nm of the device. However, the ION/IOFF ratio is improved, when Hg and Wg are downscaled from 8 to 6 nm and 18 to 12 nm, respectively.
Enhancement Performance of High Electron Mobility Transistor (HEMT) Based on Dimensions Downscaling Firas Natheer Abdul-kadir, , Nawfal Y. Jamil, Laith M. Al Taan, Waheb A. Jabbar International Journal of Electrical and Electronic Engineering and Telecommunications, 2023 This paper aims to enhance the performance of the High Electron Mobility Transistor (HEMT) according to downscaling dimensions based on the electrical properties and semiconductor materials (GaN, Si3N4, ALGaN and Si). This is to solve difficulties with reducing dimensions and ensuring HEMT has the highest performance possible. This goal was met when the physical scaling restrictions of channel diameters for different HEMTs were concurrently shrunk without compromising their performance. A simula-tion study was done using four variable factors (length, width, of the channel and length, width of the source and drain). Three electrical characteristics were used to assess the impact of altering dimensions on the performance of each kind of HEMT: threshold voltage Vt, ON-state/OFF-state current (ION/IOFF) ratio, and transconductance gm. To conduct experimental simulations under the specified situation, the well-known Silvaco TCAD simulation tool was used. The acquired simulation results revealed that the optimum performance for the downscaling device was achieved at the channel length of 1.6μm, the channel width of 0.3μm, the length of source and drain is 0.4μm and finally the width of source and drain is 0.05 μm.
Characterization of silicon tunnel field effect transistor based on charge plasma Firas Natheer Abdul-kadir, Faris Hassan Taha Indonesian Journal of Electrical Engineering and Computer Science, 2022 The aim of the proposed paper is an analytical model and realization of the characteristics for tunnel field-effect transistor (TFET) based on charge plasma (CP). One of the most applications of the TFET device which operates based on CP technique is the biosensor. CP-TFET is to be used as an effective device to detect the uncharged molecules of the bio-sample solution. Charge plasma is one of some techniques that recently invited to induce charge carriers inside the devices. In this proposed paper we use a high work function in the source (ϕ=5.93 eV) to induce hole charges and we use a lower work function in drain (ϕ=3.90 eV) to induce electron charges. Many electrical characterizations in this paper are considered to study the performance of this device like a current drain (ID) versus voltage gate (Vgs), ION/IOFF ratio, threshold voltage (VT) transconductance (gm), and sub-threshold swing (SS). The signification of this paper comes into view enhancement the performance of the device. Results show that high dielectric (K=12), oxide thickness (Tox=1 nm), channel length (Lch=42 nm), and higher work function for the gate (ϕ=4.5 eV) tend to best charge plasma silicon tunnel field-effect transistor characterization.
Temperature characteristics of Gate all around nanowire channel Si-TFET Firas Natheer Abdul-kadir Agha, Yasir Hashim, Waheb Abduljabbar Shaif Abdullah Journal of Physics Conference Series, 2021 This paper study the impact of working temperature on the electrical characteristics of gate all around nanowire channel Si-TFET and examines the effect of working temperature on threshold voltage, transcondactance (gm), ION/IOFF ratio, drain induced barrier lowering (DIBL), and sub-threshold swing (SS). The (Silvaco) simulation tool has been used to investigate the working temperature on the Si-TFET characteristics. The temperature range in this study is from -25 to 150°C. The results indicate that the TFET must work in electronic circuits with the lower temperature as possible to get better performances. Furthermore, the TFET has good performances as a temperature nanosensor with diode connection mode under ON conditions.
Review of Nanosheet Transistors Technology Firas N. A. Hassan Agha, Yasir H. Naif, Mohammed N. Shakib Tikrit Journal of Engineering Sciences, 2021 Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this review, the structure and characteristics of Nano-Sheet FET (NSFET), FinFET and NanoWire FET (NWFET) under 5nm technology node are presented and compared. According to the comparison, the NSFET shows to be more impregnable to mismatch in ON current than NWFET. Furthermore, as comparing with other nano-dimensional transistors, the NSFET has the superior control of gate all-around structures, also the NWFET realize lower mismatch in sub threshold slope (SS) and drain induced barrier lowering (DIBL).
Electrical characterization of si nanowire GAA-TFET based on dimensions downscaling Firas Natheer Abdul-Kadir, Yasir Hashim, Muhammad Nazmus Shakib, Faris Hassan Taha International Journal of Electrical and Computer Engineering, 2021 This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (VT). These parameters are critical factors of the characteristics of tunnel field effect transistors. The Silvaco TCAD has been used to study the electrical characteristics of Si-NW TFET. Output (gate voltage-drain current) characteristics with channel dimensions were simulated. Results show that 50nm long nanowires with 9nm-18nm diameter and 3nm oxide thickness tend to have the best nanowire tunnel field effect transistor (Si-NW TFET) characteristics.
Investigation and design of ion-implanted MOSFET based on (18 nm) channel length Firas Natheer Abdul-kadir, Khalid khaleel Mohammad, Yasir Hashim Telkomnika Telecommunication Computing Electronics and Control, 2020 The aim of this study is to invistgate the characteristics of Si-MOSFET with 18 nm length of ion implemented channel. Technology computer aided design (TCAD) tool from Silvaco was used to simulate the MOSFET’s designed structure in this research. The results indicate that the MOSFET with 18 nm channel length has cut-off frequency of 548 GHz and transconductance of 967 μS, which are the most important factors in calculating the efficiency and improving the performance of the device. Also, it has threshold voltage of (-0.17 V) in addition obtaining a relatively small DIBL (55.11 mV/V). The subthreshold slope was in high value of 307.5 mV/dec. and this is one of the undesirable factors for the device results by short channel effect, but it does not reduce its performance and efficiency in general.
Evaluation and Optimization of Novel Graphene Nanosheet FET: Analog/RF Perspectives Firas Natheer Abdul-Kadir Agha, Khalid Khaleel Mohammad, Hussein Ali Al ... International Journal of Electrical and Electronic Engineering and … , 2026 2026.0
Influence of Temperature on Nanosheet FET Performances FNA Agha, K Mohammed, HAAL Abdulqader, B Smaani 2025 2nd International Conference on Electronic and Computer Engineering … , 2025 2025.0
Down scaling Impact on The ION/IOFF Ratio of Nanosheet FET Digital Applications FN Agha, KK Mohammed, HA Abdulqader, B Smaani 2025 15th International Conference on Electrical Engineering, ICEENG 2025 , 2025 2025.0 Citations: 1
REVIEW ON PERFORMANCE PERSPECTIVES OF DIELECTRIC MATERIALS USED IN ADVANCED SEMICONDUCTOR DEVICES FOR VARIOUS APPLICATIONS F Agha REVIEW ON PERFORMANCE PERSPECTIVES OF DIELECTRIC MATERIALS USED IN ADVANCED … , 2025 2025.0
Enhancement Performance of High Electron Mobility Transistor (HEMT) Based on Dimensions Downscaling FN Abdul-kadir, NY Jamil, LM Al Taan, W Abdullah International Journal of Electrical and Electronic Engineering … , 2023 2023.0 Citations: 8
Characterization of silicon tunnel field effect transistor based on charge plasma FN Abdul-kadir, FH Taha Indonesian Journal of Electrical Engineering and Computer Science 25 (1 … , 2022 2022.0 Citations: 6
Review of nanosheet transistors technology ,Agha FNAK, Shakib, Mohammed Tikrit Journal of Engineering Sciences 28 (1), 40-48 , 2021 2021.0 Citations: 22
Temperature characteristics of Gate all around nanowire channel Si-TFET F Natheer Abdul-kadir Agha, Y Hashim, W Abduljabbar Shaif Abdullah Journal of Physics: Conference Series 1755 (1), 012045 , 2021 2021.0 Citations: 10
Temperature Impact on The ION/IOFF Ratio of Gate All Around Nanowire TFET FNA Agha, Y Hashim, MN Shakib 2020 IEEE International Conference on Semiconductor Electronics (ICSE), 64~61 , 2020 2020.0 Citations: 10
Investigation and design of ion-implanted MOSFET based on (18 nm) channel length FN Abdul-kadir, K Mohammad, Y Hashim TELKOMNIKA (Telecommunication, Computing, Electronics and Control) 18 (5 … , 2020 2020.0 Citations: 11
Electrical characterization of si nanowire GAA-TFET based on dimensions downscaling FNA ,Mohammed Nazmus, Yasir Hashim, Faris Hassan Taha International Journal of Electrical and Computer Engineering 11 (1), 780-787 , 2020 2020.0 Citations: 10
Optical Properties for CdSe: Cu Thin Film Prepared by Sputtering Method LM Al Taan, NY Jamil, FN Abdul-kadir Citations: 1
MOST CITED SCHOLAR PUBLICATIONS
Review of nanosheet transistors technology ,Agha FNAK, Shakib, Mohammed Tikrit Journal of Engineering Sciences 28 (1), 40-48 , 2021 2021.0 Citations: 22
Investigation and design of ion-implanted MOSFET based on (18 nm) channel length FN Abdul-kadir, K Mohammad, Y Hashim TELKOMNIKA (Telecommunication, Computing, Electronics and Control) 18 (5 … , 2020 2020.0 Citations: 11
Temperature characteristics of Gate all around nanowire channel Si-TFET F Natheer Abdul-kadir Agha, Y Hashim, W Abduljabbar Shaif Abdullah Journal of Physics: Conference Series 1755 (1), 012045 , 2021 2021.0 Citations: 10
Temperature Impact on The ION/IOFF Ratio of Gate All Around Nanowire TFET FNA Agha, Y Hashim, MN Shakib 2020 IEEE International Conference on Semiconductor Electronics (ICSE), 64~61 , 2020 2020.0 Citations: 10
Electrical characterization of si nanowire GAA-TFET based on dimensions downscaling FNA ,Mohammed Nazmus, Yasir Hashim, Faris Hassan Taha International Journal of Electrical and Computer Engineering 11 (1), 780-787 , 2020 2020.0 Citations: 10
Enhancement Performance of High Electron Mobility Transistor (HEMT) Based on Dimensions Downscaling FN Abdul-kadir, NY Jamil, LM Al Taan, W Abdullah International Journal of Electrical and Electronic Engineering … , 2023 2023.0 Citations: 8
Characterization of silicon tunnel field effect transistor based on charge plasma FN Abdul-kadir, FH Taha Indonesian Journal of Electrical Engineering and Computer Science 25 (1 … , 2022 2022.0 Citations: 6
Down scaling Impact on The ION/IOFF Ratio of Nanosheet FET Digital Applications FN Agha, KK Mohammed, HA Abdulqader, B Smaani 2025 15th International Conference on Electrical Engineering, ICEENG 2025 , 2025 2025.0 Citations: 1
Optical Properties for CdSe: Cu Thin Film Prepared by Sputtering Method LM Al Taan, NY Jamil, FN Abdul-kadir Citations: 1
Evaluation and Optimization of Novel Graphene Nanosheet FET: Analog/RF Perspectives Firas Natheer Abdul-Kadir Agha, Khalid Khaleel Mohammad, Hussein Ali Al ... International Journal of Electrical and Electronic Engineering and … , 2026 2026.0
Influence of Temperature on Nanosheet FET Performances FNA Agha, K Mohammed, HAAL Abdulqader, B Smaani 2025 2nd International Conference on Electronic and Computer Engineering … , 2025 2025.0
REVIEW ON PERFORMANCE PERSPECTIVES OF DIELECTRIC MATERIALS USED IN ADVANCED SEMICONDUCTOR DEVICES FOR VARIOUS APPLICATIONS F Agha REVIEW ON PERFORMANCE PERSPECTIVES OF DIELECTRIC MATERIALS USED IN ADVANCED … , 2025 2025.0
