Dr. C Gangaiah Yadav
@cbit.edu.in
Associate Professor, ECE
Chaitanya Bharathi Institute of Technology
RESEARCH, TEACHING, or OTHER INTERESTS
Electrical and Electronic Engineering, Signal Processing
Scopus Publications
Scopus Publications
M. Venkatesh, V. G. Sivakumar, C. Gangaiah Yadav, B. Gopi, N. Malathi, and S. Velmurugan
IEEE
Microgrid systems have emerged because of the rising need for efficient and dependable power supply, as well as the widespread use of internet of things (IoT) technologies. However, nonlinear loads, fluctuations in voltage, and harmonics are often present in these systems, resulting in poor power quality. This research proposes a Unified Power Quality Conditioner (UPQC) system to overcome these obstacles. The adaptive neuro-fuzzy inference system is employed with IoT connection that allows the UPQC to dynamically adapt in real-time to power quality issues, keeping important loads supplied with clean, uninterrupted power. The suggested system is shown to be beneficial in preventing power outages by providing continuous monitoring, control, and problem diagnostics. The results set the way for future power supply solutions that are more efficient and dependable by adding to a set of information regarding methods to improve power quality in microgrid systems.
C. Gangaiah Yadav, C. Keerthi, and A. Kiran Kumari
Springer Nature Singapore
C.Gangaiah Yadav*, , K.S.Vijula Grace, and
Blue Eyes Intelligence Engineering and Sciences Engineering and Sciences Publication - BEIESP
An aggressive scaling of the technology and the increasing the number of the transistor counts are the major challenge of the design of the Integrated Circuit (IC). As well as interconnection lines and resistive opens have become a problem in modern nanometre technologies. The resistive open faults denote degradation in the connectivity within a circuit’s interconnects because of unavoidable manufacturing failures in both current and developing technologies. The resistive open fault is an imperfect circuit connection that can be modelled as a defect resistor between two circuit nodes. The Resistive open faults will not cause function fault immediately. But, it will cause the delay fault and cannot employ the design of voltage to survey. In this research, find the impact of resistive open fault in the 7-Transistor (7T) SRAM cell design and inverter chain. The proposed 7T SRAM cell design and inverter chain is implemented in 45nm technology with cadence library. The main objective of this proposed research work is to efficiently detect impact of resistive open faults and reduces delay and static and dynamic power of 7T SRAM cell design and inverter chain.
Gangaiah C. Yadav and Vijula K. S. Grace
American Scientific Publishers
Resistive open fault represents degradation in conductivity within a circuit interconnection. Due to this manufacturing failure occurs in IC interconnection. Such fault causes performance failures and reliability risk. This paper presents the analysis various detection methods for resistive open faults. And detectable resistance range versus VDD varies with the test speed also observes. Depending on test speed and small delay faults Multi-VDD is required for detection of ROFs.