GOKURAJU THRIVENI

@christuniversity.in

Assistant Professor and Electronics & Communication Engineering
CHRIST (Deemed to be University)

GOKURAJU THRIVENI


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https://researchid.co/gokurajuthriveni

RESEARCH INTERESTS

Numerical modeling and simulation aspects of nanoelectronic devices, Worked on Double gate high-k MOSFETs, Strained Silicon MOSFETs, Ultra sensitive Hydrogen gas sensor, Graphene FET for biosensing applications.
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Scopus Publications

Scopus Publications

  • Optimal design of controller for automatic voltage regulator performance enhancement: a survey
    Athira Sivanandhan, Gokuraju Thriveni
    Electrical Engineering, 2024
  • Antifouling Nanoparticle Coatings for Post-Harvest Food Preservation
    Gokuraju Thriveni, Hari Murthy, CH. Anusha
    Novel Anti Corrosion and Anti Fouling Coatings and Thin Films, 2024
  • Advancement and Challenges of Biosensing Using Field Effect Transistors
    Gokuraju Thriveni, Kaustab Ghosh
    Biosensors, 2022
    Field-effect transistors (FETs) have become eminent electronic devices for biosensing applications owing to their high sensitivity, faster response and availability of advanced fabrication techniques for their production. The device physics of this sensor is now well understood due to the emergence of several numerical modelling and simulation papers over the years. The pace of advancement along with the knowhow of theoretical concepts proved to be highly effective in detecting deadly pathogens, especially the SARS-CoV-2 spike protein of the coronavirus with the onset of the (coronavirus disease of 2019) COVID-19 pandemic. However, the advancement in the sensing system is also accompanied by various hurdles that degrade the performance. In this review, we have explored all these challenges and how these are tackled with innovative approaches, techniques and device modifications that have also raised the detection sensitivity and specificity. The functional materials of the device are also structurally modified towards improving the surface area and minimizing power dissipation for developing miniaturized microarrays applicable in ultra large scale integration (ULSI) technology. Several theoretical models and simulations have also been carried out in this domain which have given a deeper insight on the electron transport mechanism in these devices and provided the direction for optimizing performance.
  • Covalent functionalization in graphene nanoribbon: Theoretical modeling and sensitivity analysis
    G. Thriveni, Kaustab Ghosh
    Journal of Applied Physics, 2021
    The alteration of electronic properties in chemically modified graphene can be utilized for chemical and biosensing applications. Thus, it is essential to understand how the alteration of density of states and conductance spectra of functionalized zigzag and armchair graphene nanoribbon (GNR) affects its sensitivity. In this aspect, the current–voltage characteristics of GNR based sensors are modeled using the non-equilibrium Green's function method. Our findings show that the presence of chemical moiety at one edge of the zigzag GNR structure opens the bandgap that reduces the current conduction and enhances the sensitivity for detection. However, double edge functionalization restores the semi-metallic character of the zigzag ribbon that reduces the sensitivity. Both single and double edge atomic substitution in armchair ribbon makes it n-type, which shows the alteration in current conduction for detecting the presence of the chemical species. We further found that increasing the width of the ribbon decreases the device sensitivity while it increases for the double edge substituted zigzag structure. The study thus provides essential information and insights into utilizing and operating different edge structures of graphene based sensors for effective detection of chemical and biomolecular species.
  • Theoretical analysis and optimization of high-k dielectric layers for designing high-performance and low-power-dissipation nanoscale double-gate MOSFETs
    G. Thriveni, Kaustab Ghosh
    Journal of Computational Electronics, 2019
  • Performance analysis of nanoscale double gate strained silicon MOSFET with high k dielectric layers
    G Thriveni, Kaustab Ghosh
    Materials Research Express, 2019
    This study presents a theoretical model to describe the combined characteristics of strained silicon nanoscale double gate MOSFET along with high k dielectric layer. Although a well- tempered MOSFET with strong gate electrostatics can be devised using high k gate material, lower conduction band offset (CBO) over silicon results in leakage and subsequent static power dissipation. The study shows that this effect can reduce the Ion/Ioff ratio to 2 × 102 with 2 nm thick TiO2 dielectric layer (k = 60) along with mobility degradation. Incorporating the effects of strained silicon and high k dielectrics in MOSFETs exhibits bandstructure alteration and increase in CBO. This inhibits carrier tunnelling causing leakage with restoration of Ion/Ioff ratio to 4.5 × 106. The mobility can also be improved along with the maintenance of effective gate electrostatics. Thus the study illustrates the possibility of designing the nanoscale MOS devices with all the essential characteristics without trade-off over other performance parameters.
  • Choice of Gate Insulator for Tunnelling Current Minimization and Effective Gate Electrostatics in Double Gate Nanoscale Mosfet
    G. Thriveni, Kaustab Ghosh
    Proceedings of the 4th International Conference on Devices Circuits and Systems Icdcs 2018, 2019
    A numerical model using self consistent Poisson's equation solver is presented to elucidate the potential profile and current-voltage characteristics of double gate nanoMOSFET using 32nm technology. Here we have explored the performance of the nanodevice with different dielectric layers. The focus of this work is to identify the type of gate dielectric material which is capable enough to control the electrostatics across the channel through gate bias and reduce the tunneling current. We find that $\\mathrm {T}\\mathrm {i}\\mathrm {O}_{2}$ layer having k=80 produces higher tunneling current through gate leakage although it exhibited stronger gate control on the channel conduction. A combination of $\\mathrm {T}\\mathrm {i}\\mathrm {O}_{2}$ and $\\mathrm {S}\\mathrm {i}\\mathrm {O}_{2}$ dielectric layers is proposed to mitigate tunnelling in these devices and improve its performance.