Harshit Kansal

@harshitk@iiserb.ac.in

Research Associate
indian institute of science education and research bhopal



              

https://researchid.co/harshitkansal6988

RESEARCH, TEACHING, or OTHER INTERESTS

Electrical and Electronic Engineering, Electrical and Electronic Engineering, Engineering

18

Scopus Publications

44

Scholar Citations

4

Scholar h-index

1

Scholar i10-index

Scopus Publications

  • A negative capacitance field effect transistor with a modified gate stack and drain-side cavity for label-free biosensing
    Harshit Kansal and Aditya Sankar Medury
    IOP Publishing
    Abstract Dielectrically modulated (DM) negative capacitance field effect transistor (NCFET)-based label-free biosensors have emerged as promising devices for accurate detection of various biomolecules, where the sensitivity of DM architectures strongly depends on the sensing mechanism as well as on the size of the nanocavity. Therefore, to achieve higher sensitivity along with reduced fabrication complexity, we propose to utilize a pre-existing drain-side spacer region as a nanocavity, in a fully depleted silicon-on-insulator-based NCFET architecture. The ferroelectric (FE) layer in the metal-ferroelectric-insulator-semiconductor configuration meaningfully alters the impact of the drain’s electric field on the source-side electrostatics, which results in higher sensitivity. Having quantified the sensitivity of an FE-dielectric (FE-DE) gate-stack-based NCFET biosensor, we now propose to include a paraelectric (PE) layer between the FE and DE materials, thus modifying the gate stack from FE-DE to FE-PE-DE with an equivalent negative capacitance seen from both stacks; here, a remarkable improvement is seen in the FE-PE-DE gate-stack-based NCFET, with nearly identical linearity performance, as seen from the high Pearson’s coefficient value ( r 2 ⩾ 0.9). Therefore, to illustrate the efficacy of the proposed sensing mechanism and the modified gate stack (FE-PE-DE), DE constant ( k Bio ) values in the range of k Bio = 4.5 to k Bio = 75.99 are considered. Finally, the effect of scaling the channel length ( L g ) on the sensitivity of the FE-PE-DE NCFET device is shown, and a high value, particularly at lower permittivity, demonstrates the versatility and wide applicability of the proposed NCFET biosensor.

  • Algorithm for Calibrating Effective Mass Parameters to consider Quantum Confinement Effects in Ultra-Thin-Body Devices for Various Temperatures
    Nalin Vilochan Mishra, Harshit Kansal, Yogesh Dhote, Ravi Solanki, and Aditya Sankar Medury
    Springer Science and Business Media LLC

  • Band-structure based electrostatics model for ultra-thin-body double-gate silicon-on-insulator MOS devices
    Nalin Vilochan Mishra, Harshit Kansal, Ravi Solanki, and Aditya Sankar Medury
    IOP Publishing
    Abstract The effect of quantum confinement has become significant in terms of its impact on the scalability and electrostatics of ultra-thin-body double-gate MOSFETs. In this paper, we present a simplified model to account for the effect of quantum confinement, considering the contribution of the ground-state and the first excited state of the conduction band, on the electron carrier concentration, which when incorporated into the 1-D Poisson’s equation, enables the determination of the electrostatic potential. We establish the accuracy of the proposed model, over a wide range of process and electrical parameters, through aggressively benchmarking the electrostatics parameters obtained from the proposed model with results from the sp 3 d 5 s ∗ tight-binding method (TBM), over a wide range of device temperatures. Furthermore, a simplified model for the integrated channel charge density is shown in the form of a diffusion layer charge where the thickness and potential of this layer, while being gate voltage dependent, enables the channel charge density obtained from the model to agree well with results from TBM. Through this physics based and accurate model for the integrated charge, a simplified understanding of the gate capacitance is shown as a series combination of the diffusion layer capacitance, strong-inversion capacitance and oxide capacitance, which includes the effects of structural confinement as well as charge confinement at low and high gate voltages, respectively.



  • The Impact of a Paraelectric layer in the FE/DE Stack on Performance of NCFET
    Harshit Kansal and Aditya Sankar Medury
    Springer Science and Business Media LLC

  • Temperature Dependent Band Gap Correction Model Using Tight-Binding Approach for UTB Device Simulations
    Nalin Vilochan Mishra, Ravi Solanki, Harshit Kansal, and Aditya Sankar Medury
    Institute of Electrical and Electronics Engineers (IEEE)
    In order to accurately determine the electrostatics of Ultra-Thin-Body (UTB) devices, the semi-empirical tight-binding (TB) approach is widely used for calculating the channel thickness dependent band structure of any material at those temperatures where TB parameters are available (generally defined at 0 K and 300 K). In this work, we analyze the variation of band structure for Si, Ge, and GaAs over different channel thicknesses at 0 K and 300 K, and show that the band curvature at the band minima remains unchanged with temperature, while the band gap changes significantly and affects the channel electrostatics. Based on this finding, we propose an approach to simulate the electrostatics of UTB devices, at any temperature between 0 K and 300 K, using the band structure obtained at 0 K, along with a suitable channel thickness and temperature-dependent band gap correction. From the results obtained for the channel charge density, we show good agreement with band structure based simulation results, at 300 K, over a wide range of channel thicknesses, for Si, Ge, and GaAs, while also showing good agreement with TCAD simulation results, at a typical intermediate temperature of 150 K, thus highlighting the accuracy, simplicity and wide applicability of the proposed approach.


  • Improved analog performance of FDSOI based NCFET with a ferroelectric-paraelectric-dielectric gate stack
    Harshit Kansal and Aditya Sankar Medury
    IOP Publishing
    Abstract With the superior analog/RF performance of planar device architectures such as fully depleted silicon-on-insulator (FDSOI) MOSFETs, it becomes important to investigate the impact of a ferroelectric material in the gate stack, resulting in negative capacitance (NC) behavior, on the device performance. In this work, through calibrating the FDSOI MOSFET (as the baseline device architecture) with experimental data, we compare the impact of ferroelectric–dielectric (FE–DE) and ferroelectric–paraelectric–dielectric (FE–PE–DE) gate stacks on the electrostatics of an NCFET device for a practically realisable metal–ferroelectric–insulator–semiconductor (MFIS) structure. A suitable thickness of the ferroelectric (FE) layer in the FE–DE stack and the maximum drain–source voltage ( V d s ) that can be applied (determining the power supply voltage), are identified so as to ensure that constraints such as no negative differential resistance (NDR) effects, threshold voltage ( V t h ), sub-threshold slope (SS) invariability with drain voltage variations and hysteresis-free behavior in transfer characteristics ( I d – V g s ) are all satisfied. From the thickness of the FE layer in the FE–DE stack, the thickness of the FE layer in the FE–PE–DE stack (PE layer thickness is fixed at 1 nm) is determined where with a thicker FE layer, we obtain similar capacitance from the FE–PE–DE gate stack to that obtained from the FE–DE stack, while meeting all the constraints applied to the FE–DE stack based NCFET, enabling determination of the power supply voltage. Through showing good SSs with reduced output conductance ( g d s ), resulting in improved dc gain ( g m g d s ) and improved linearity parameters ( g m 2 and g m 3 ) along with scaling of power supply, an FE–PE–DE stack shows better analog performance, with lower power consumption, compared to an FE–DE stack, for an FDSOI NCFET, at 14 nm gate length.

  • Negative capacitance partially junction-less FET for hysteresis-free and improved analog performance
    Harshit Kansal and A. S. Medury
    IOP Publishing
    Abstract Given the advantage of high transconductance (g m) at low gate voltages (V gs), seen in junction-less (JL) transistors, it becomes important to incorporate these advantages in conventional bulk MOSFETs which have thus far been used extensively for analog circuit applications. In this work, we propose a partially JL channel in a bulk MOSFET device, which when investigated for a metal-ferroelectric-insulator-semiconductor (MFIS) with negative capacitance field-effect transistor (NCFET) shows superior analog device performance, with improved scalability. Through technology computer aided design (TCAD)-based transient simulations, we identify an optimum and almost constant ferroelectric layer thickness for different gate lengths, which enables hysteresis-free behavior, along with reasonably steep sub-threshold slopes (SS), that meets international roadmap for devices and systems specifications. For this device, we then determine the maximum drain voltage, V ds, which ensures no drain-induced barrier raise effects, based on which improved transconductance generation efficiency (g m/I d), with minimal gate induced drain leakage is shown.

  • Comparison of Different Approaches used for Estimation of Electrostatics in UTB devices
    Nalin Vilochan Mishra, Harshit Kansal, Ravi Solanki, and Aditya Sankar Medury
    IEEE
    With the scaling of SOI channel and oxide thicknesses in Ultra-thin Body (UTB) devices, Quantum Confinement Effects (QCEs) becomes significant and need to be considered for accurate estimation of electrostatics parameters such as electron density inside the channel. In this work, we propose to use a $sp^{3}d^{5}s^{\\ast}$ Tight-Binding (TB) scheme by suitably selecting the significant k-points around the band minima, which makes this approach computationally efficient while being accurate to account for Quantum Confinement Effects. Thus through comparison of electrostatics obtained from other approaches, such as Effective Mass Approximation (EMA) used by SCHRED and Density Gradient Approach (DGM) used in TCAD, we show the importance of using the TB based approach as it is shown to be far more accurate in considering Quantum confinement effects compared to other existing approaches.

  • Confinement Effect and Conduction Band Offset in DG-SOI MOSFETs: A Simulation Study
    Harshit Kansal, Nalin Vilochan Mishra, and Aditya Sankar Medury
    IEEE
    Besides Quantum Confinement Effects (QCEs) seen in Ultra-Thin (UT) channel Double-Gate Silicon on Insulator (DG-SOI) MOS devices, the Band-offset variations between the oxide and the UT channel also impact device electrostatics, which is not adequately considered by the existing TCAD Models. Effective Mass Approximation (EMA) is one of the widely used approach which takes both QCEs and Conduction Band offset (CBO) variations into account. In this work, we ensure the accuracy of the EMA approach through benchmarking the results with the Tight-Binding Method (TBM), for an infinite potential well (equivalent to considering high CBO) case. Having corrected effective mass while also inserting suitable energy correction parameters, the accuracy of the EMA approach is now ensured. In this work, we show that by reducing the band-gap of the oxide material, the integrated charge density obtained using the Direct Tunneling (DT) model in TCAD can now accurately emulate the results obtained from the benchmarked Effective Mass Approximation (EMA) approach.

  • Hysteresis-free Behavior and Improved Performance of Negative Capacitance Optimized Bulk MOSFET
    Harshit Kansal and Aditya Sankar Medury
    IEEE
    Despite the use of High-k gate stacks, poor channel electrostatics at short channel lengths has limited the applicability of conventional Bulk MOSFETs. In this paper, we firstly present the design of an optimized N-channel Partially Junction-less Bulk MOSFET with a view to suppressing various leakage mechanisms, while also taking channel quantization effects into account. Through detailed process simulations, the process steps required to achieve the identical transfer characteristics are determined, thus providing a more practical appraisal of the feasibility of the device, where the threshold voltage (Vth), sub-threshold slope (SS) and ION/IoFF ratio are nearly identical for both the devices. Furthermore, through the inclusion of ferroelectric layer of suitable thickness over the existing gate stack, we show a significant improvement in the device performance, while ensuring hysteresis-free behavior in transfer characteristics.

  • TCAD based Modeling of Sub-surface Leakage in Short Channel Bulk MOSFETs
    Harshit Kansal and Aditya Sankar Medury
    IEEE
    Aggressive scaling of the channel length of Bulk MOSFETs manifests in higher sub-surface leakage current, which becomes an increasingly significant component of the OFF-State leakage current. By firstly identifying the sub-surface leakage region as one that manifests in a region away from the electrostatic control of the gate, but, within the source/drain junction depth, while being impacted by the drain voltage, we model the sub-surface leakage current using a non-charge-sheet based approach, which is further simplified as a physics-based semi-analytical model similar to the Shockley equation of an ideal ‘forward-biased’ p-n junction diode. In addition to validating the proposed model, we also show the impact of various structural and electrical parameters, thus demonstrating that the model provides key insights on device behaviour.

  • Improved short channel electrostatics through design of partially junction-less double-gate MOSFETs
    Harshit Kansal and Aditya Sankar Medury
    AIP Publishing
    Quantum confinement effects tend to diminish gate control over the channel, further degrading the channel electrostatics of short channel Double-Gate (DG) Silicon-on-Insulator (SOI) MOSFETs. In this work, we first design an n-channel Junction-less (JL) DG MOSFET with a channel length (Lg) of 10 nm, where the source/drain doping, determined through Technology Computer-Aided Design (TCAD) simulations, enables better gate control for different channel thicknesses (tch) and oxide thicknesses (tox). The source/drain doping, thus determined, enables JL DG MOSFETs to overcome quantum confinement effects while also achieving key ITRS (International Technology Roadmap for Semiconductors) targets in terms of sub-threshold slope (S) and threshold voltage (Vth). We then introduce a heavily doped symmetric p-type silicon layer at the interface of the channel region with the top/bottom oxide such that the thickness and doping of the p-type layer enable tuning of the threshold voltage. In this partially JL DG MOSFET, by replacing the n-type doped silicon with n-type silicon–germanium (Si0.7Ge0.3) of lower doping, determined through TCAD simulations, we continue to demonstrate excellent channel electrostatics (ITRS targets) at short channel lengths (Lg = 10 nm) over a wide range of channel and oxide thicknesses while also showing enhanced strong inversion channel currents.

  • Towards Novel Channel Doping Profiles in Short Channel Bulk MOSFETs for OFF-State Current Reduction and Superior Channel Electrostatics
    Harshit Kansal and Aditya Sankar Medury
    IEEE
    For short channel MOS Transistors, leakage current flowing underneath the Si/SiO2 interface (sub-surface leakage) both within the source-drain junction depth, as well as the current flowing through the bulk, are found to significantly contribute to the OFFState current (IOFF). Through TCAD Simulations, we firstly identify the region most susceptible to sub-surface leakage and then compare channel doping profiles such as the Uniformly doped (UD) and Super-Steep Retrograde (SSR), with a view to reducing IOFF. This comparison enables us to propose a novel doping profile in the channel, demonstrating a higher ON-State current (ION) compared to the SSR channel doping, while showing a comparable OFF-State current, both for Vds = 0.05 V and Vds = 1 V.

  • Short-channel effects and sub-surface behavior in bulk MOSFETs and nanoscale DG-SOI- MOSFETs: A TCAD investigation
    Harshit Kansal and Aditya Sankar Medury
    IEEE
    Using TCAD simulations, we have identified the existence of a sub-surface conducting region, below the Si/SiO2 interface, with significant electron concentration, in short channel bulk MOSFETs (p-type silicon substrate), at high accumulation bias. This is symptomatic of weakening gate control. The electron concentration in this sub-surface region is shown to be dependent on oxide thickness, channel length and source-drain junction depth. In the case of short channel nanoscale Double Gate SOI (DGSOI) MOSFETs, studied for different SOI channel thicknesses, despite quantum confinement effects, the electron concentration is found to be considerably reduced at lower SOI channel thicknesses, compared to Bulk MOSFETs.

  • Quantum confinement effects and electrostatics of planar nano-scale symmetric double-gate soi MOSFETs
    Aditya Sankar Medury and Harshit Kansal
    IEEE
    The effects of quantum confinement on the charge distribution in planar Double-Gate (DG) SOI (Silicon-on-Insulator) MOSFETs were examined, for sub-10 nm SOI film thicknesses $({\\mathrm {t_{si}}}\\ \\leq\\ 10\\ nm)$, by modeling the potential experienced by the charge carriers as that of an an-harmonic oscillator potential, consistent with the inherent structural symmetry of nanoscale symmetric DGSOI MOSFETs. By solving the 1-D Poisson’s equation using this potential, the results obtained were validated through comparisons with TCAD simulations. The present model satisfactorily predicted the electron density and channel charge density for a wide range of SOI channel thicknesses and gate voltages.

RECENT SCHOLAR PUBLICATIONS

  • Negative Capacitance Field Effect Transistor with Modified Gate Stack and Drain-sided cavity for Label-free Biosensing
    H Kansal, AS Medury
    Semiconductor Science and Technology 2024

  • Algorithm for Calibrating Effective Mass Parameters to consider Quantum Confinement Effects in Ultra-Thin-Body Devices for Various Temperatures
    NV Mishra, H Kansal, Y Dhote, R Solanki, AS Medury
    Journal of Electronic Materials, 1-9 2023

  • Engineering negative capacitance Fully Depleted Silicon-on-insulator FET for improved performance
    H Kansal, AS Medury
    Microelectronics Journal 140, 105917 2023

  • Band-structure based electrostatics model for ultra-thin-body double-gate silicon-on-insulator MOS devices
    NV Mishra, H Kansal, R Solanki, AS Medury
    Journal of Physics D: Applied Physics 56 (41), 415102 2023

  • Analysis and Mitigation of Negative Differential Resistance effects in Double-Gate Silicon-on-Insulator Negative Capacitance Field Effect Transistor with improved analog
    M Pratap, H Kansal, AS Medury
    Microelectronics Journal 136, 105777 2023

  • The Impact of a Paraelectric layer in the FE/DE Stack on Performance of NCFET
    H Kansal, AS Medury
    Silicon 15 (4), 1961-1966 2023

  • Temperature dependent band gap correction model using tight-binding approach for UTB device simulations
    NV Mishra, R Solanki, H Kansal, AS Medury
    IEEE Transactions on Nanotechnology 22, 8-13 2022

  • Confinement Effect and Conduction Band Offset in DG-SOI MOSFETs: A Simulation Study
    H Kansal, NV Mishra, AS Medury
    2022 International Semiconductor Conference (CAS), 281-284 2022

  • FE/PE/DE gate stack enabling improved analog performance in partially Junction-less NCFETs
    H Kansal, AS Medury
    Microelectronics Journal 128, 105571 2022

  • Improved analog performance of FDSOI based NCFET with a ferroelectric–paraelectric–dielectric gate stack
    H Kansal, AS Medury
    Semiconductor Science and Technology 37 (10), 105007 2022

  • Negative capacitance partially junction-less FET for hysteresis-free and improved analog performance
    H Kansal, AS Medury
    Japanese Journal of Applied Physics 61 (8), 085003 2022

  • Comparison of Different Approaches used for Estimation of Electrostatics in UTB devices
    NV Mishra, H Kansal, R Solanki, AS Medury
    2022 IEEE 22nd International Conference on Nanotechnology (NANO), 347-350 2022

  • Hysteresis-free Behavior and Improved Performance of Negative Capacitance Optimized Bulk MOSFET
    H Kansal, AS Medury
    2022 IEEE Silicon Nanoelectronics Workshop (SNW), 1-2 2022

  • Analysis of Conduction Band Offset Variation on the Electrostatics of UTB Devices through the Modified Effective Mass Approximation (mEMA)
    H Kansal, N Vilochan Mishra, R Solanki, AS Medury
    TechRxiv 2022

  • TCAD based modeling of sub-surface leakage in short channel bulk MOSFETs
    H Kansal, AS Medury
    2021 Joint International EUROSOI Workshop and International Conference on 2021

  • Improved short channel electrostatics through design of partially junction-less double-gate MOSFETs
    H Kansal, AS Medury
    AIP advances 11 (2) 2021

  • Towards novel channel doping profiles in short channel bulk mosfets for off-state current reduction and superior channel electrostatics
    H Kansal, AS Medury
    2020 IEEE Silicon Nanoelectronics Workshop (SNW), 105-106 2020

  • Quantum confinement effects and electrostatics of planar nano-scale symmetric double-gate SOI MOSFETs
    AS Medury, H Kansal
    2019 IEEE International Conference on Electron Devices and Solid-State 2019

  • Short-Channel Effects and Sub-Surface Behavior in Bulk MOSFETs and Nanoscale DG-SOI-MOSFETs: A TCAD Investigation
    H Kansal, AS Medury
    2019 Silicon Nanoelectronics Workshop (SNW), 1-2 2019

MOST CITED SCHOLAR PUBLICATIONS

  • Temperature dependent band gap correction model using tight-binding approach for UTB device simulations
    NV Mishra, R Solanki, H Kansal, AS Medury
    IEEE Transactions on Nanotechnology 22, 8-13 2022
    Citations: 10

  • Quantum confinement effects and electrostatics of planar nano-scale symmetric double-gate SOI MOSFETs
    AS Medury, H Kansal
    2019 IEEE International Conference on Electron Devices and Solid-State 2019
    Citations: 8

  • Improved short channel electrostatics through design of partially junction-less double-gate MOSFETs
    H Kansal, AS Medury
    AIP advances 11 (2) 2021
    Citations: 6

  • Short-Channel Effects and Sub-Surface Behavior in Bulk MOSFETs and Nanoscale DG-SOI-MOSFETs: A TCAD Investigation
    H Kansal, AS Medury
    2019 Silicon Nanoelectronics Workshop (SNW), 1-2 2019
    Citations: 5

  • Analysis and Mitigation of Negative Differential Resistance effects in Double-Gate Silicon-on-Insulator Negative Capacitance Field Effect Transistor with improved analog
    M Pratap, H Kansal, AS Medury
    Microelectronics Journal 136, 105777 2023
    Citations: 4

  • Band-structure based electrostatics model for ultra-thin-body double-gate silicon-on-insulator MOS devices
    NV Mishra, H Kansal, R Solanki, AS Medury
    Journal of Physics D: Applied Physics 56 (41), 415102 2023
    Citations: 2

  • Improved analog performance of FDSOI based NCFET with a ferroelectric–paraelectric–dielectric gate stack
    H Kansal, AS Medury
    Semiconductor Science and Technology 37 (10), 105007 2022
    Citations: 2

  • Comparison of Different Approaches used for Estimation of Electrostatics in UTB devices
    NV Mishra, H Kansal, R Solanki, AS Medury
    2022 IEEE 22nd International Conference on Nanotechnology (NANO), 347-350 2022
    Citations: 2

  • TCAD based modeling of sub-surface leakage in short channel bulk MOSFETs
    H Kansal, AS Medury
    2021 Joint International EUROSOI Workshop and International Conference on 2021
    Citations: 2

  • Engineering negative capacitance Fully Depleted Silicon-on-insulator FET for improved performance
    H Kansal, AS Medury
    Microelectronics Journal 140, 105917 2023
    Citations: 1

  • FE/PE/DE gate stack enabling improved analog performance in partially Junction-less NCFETs
    H Kansal, AS Medury
    Microelectronics Journal 128, 105571 2022
    Citations: 1

  • Towards novel channel doping profiles in short channel bulk mosfets for off-state current reduction and superior channel electrostatics
    H Kansal, AS Medury
    2020 IEEE Silicon Nanoelectronics Workshop (SNW), 105-106 2020
    Citations: 1