Himanshu Diwakar

@iitb.ac.in

Teaching Assistant
IIT Bombay

https://researchid.co/hdiwakar

EDUCATION

PhD, IIT Bombay

RESEARCH, TEACHING, or OTHER INTERESTS

Electrical and Electronic Engineering, Engineering

Scopus Publications

Scholar Citations

Scholar h-index

Scholar i10-index

Scopus Publications

Comprehensive physics-based modeling of post-cycling long-term data retention in 176L 3-D NAND Flash Memories
Karansingh Thakor, Nikhil Rangarajan, Himanshu Diwakar, Rashmi Saikia, Tarun Samadder, Souvik Mahapatra, Shyam Raghunathan, and Yingda Dong
IEEE
The contributions to long-term data retention in Charge Trap (CT) 3-D NAND from (i) Vertical Loss components, including Trap Assisted Tunneling (TAT), charge De-Trapping (DT) and interface trap passivation (ITP), and (ii) Inter-Cell components, namely Lateral Migration (LM), are studied for various Program/Erase (P/E) cycling doses and program levels (L), at different bake temperatures (TBAKE) using a physics-based Activated Barrier Double Well Thermionic (ABDWT) model. The advantages and computational efficiency of the above model with respect to the empirical stretched exponential model is illustrated by comparing the parameters required to model the overall charge loss. It is shown that the ABDWT approach can model the total charge loss with a single parameter, which varies for each contributing mechanism with cycling dose only. The physical significance of the parameter variation of each mechanism with various conditions is explained.

A TCAD Framework for HCD in n-MOSFETs for PMIC Applications
Himanshu Diwakar and Souvik Mahapatra
IEEE
Sentaurus Device TCAD is enabled to simulate the carrier and lattice heating, trap generation, and the impact of generated traps on parametric shift during Hot Carrier Degradation (HCD) stress in MOSFET. The carrier and lattice heating are calculated using Spherical Harmonics Expansion (SHE) and a coupled Drift-Diffusion (DD) with Hydrodynamic (HD) models, respectively. Trap generation is simulated by the Reaction-Diffusion-Drift (RDD) model. The coulomb scattering term of the mobility model in TCAD is suitably modified to simulate the impact of localized generated traps. The TCAD setup is validated using multi-parametric shift experimental HCD data across different stress conditions.

A Generic Framework for MOSFET Reliability - Part II: Gate and Drain Stress - HCD
Souvik Mahapatra, Himanshu Diwakar, Karansingh Thakor, Nilotpal Choudhury, Payel Chatterjee, Satyam Kumar, Udit Singhal, and Uma Sharma
Institute of Electrical and Electronics Engineers (IEEE)
The Reaction Diffusion Drift (RDD) model is incorporated in the Sentaurus Technology CAD (TCAD) framework and coupled with carrier and lattice heating to calculate the generation of traps during channel hot carrier stress. The parametric shift due to these generated defects, localized near the drain junction of the device, is calculated under different combinations of gate and drain bias stress. The developed TCAD framework is validated against measured data for devices having varying gate length, oxide thickness, and junction structure. The ability of the framework to reproduce measured time kinetics, gate and drain bias, and temperature dependence is demonstrated. The absence of recovery after hot carrier stress is explained using the stochastic implementation of the same model. A 1-D standalone version of the same model, having identical time kinetics as TCAD, together with the Bias Temperature Instability (BTI) analysis tool discussed in Part I, is used to isolate the BTI and pure Hot Carrier Degradation (HCD) contribution during HCD stress. An equivalent compact model is used for cycle-by-cycle simulation of circuit aging due to HCD in different Ring Oscillator (RO) stages, by using the framework discussed in Part I. The error associated with blanket assignment of AC-to-DC ratio is demonstrated.

Modeling of Classical Channel Hot Electron Degradation in n-MOSFETs Using TCAD
Himanshu Diwakar, Karansingh Thakor, and Souvik Mahapatra
Institute of Electrical and Electronics Engineers (IEEE)
A technology CAD (TCAD) setup is used to calculate the channel hot electron (CHE) induced parametric drift in n-MOSFETs. The setup uses reaction-diffusion-drift model and utilizes carrier energy, vertical electric field, and lattice temperature effects, to calculate the time kinetics of trap generation and its impact on the device parametric drift. Experimental data from published reports, measured using different probes, for midgate bias stress under varying drain bias (<inline-formula> <tex-math notation="LaTeX">$\\sim 3$ </tex-math></inline-formula>–8 V) and temperature (0 °C–100 °C) are modeled, in classical devices having different channel lengths (2.0–<inline-formula> <tex-math notation="LaTeX">$0.3~\\mu \\text{m}$ </tex-math></inline-formula>) and oxide thicknesses (35–5 nm). The impact of device dimension scaling on the spatial distribution of generated traps and their impact on the device parametric drift are discussed.

Modeling of Channel Hot Electron Degradation in n-MOSFETs
Karansingh Thakor, Himanshu Diwakar, and Souvik Mahapatra
IEEE
Sentaurus TCAD is enabled and used to model the time kinetics of Channel Hot Electron Degradation (CHED) in n-channel MOSFETs. The impact of stress gate (V<inf>G</inf>) and drain (V<inf>D</inf>) bias and temperature (T) is studied on devices having various gate length (L<inf>G</inf>) and oxide thickness (T<inf>OX</inf>). Measured data from devices having different L<inf>G</inf>, T<inf>OX</inf> and junction structure are modeled using TCAD, when CHED is solely due to generated traps at the overlap and channel regions. In some devices, electron trapping and generated traps in the spacer also contributes, these are handled by a suitable compact model.

Modeling Time and Bias Dependence of Classical HCD Mechanism (Peak I<inf>SUB</inf>Stress) in n-MOSFETs
Himanshu Diwakar, Karansingh Thakor, and Souvik Mahapatra
IEEE
Time and drain bias dependence of HCD under peak I<inf>SUB</inf> (V<inf>G</inf> ~ V<inf>D</inf>/2) stress are modeled. Published n-MOSFET data for different L<inf>CH</inf> (2.0µm to 37nm), T<inf>OX</inf> (35nm to 1.85nm), type of junction (HDD, LDD/HDD, SDE/HDD) and stress V<inf>D</inf> (8V to 1.6V) are analyzed. A compact model is used to model the time kinetics and to explain its difference (i.e., power law or non-power law) in devices having different types of junctions. The dominant energy model is used for V<inf>D</inf> dependence, and the model parameters are obtained with scaling. The time kinetics and V<inf>D</inf> dependence are also modeled using TCAD simulations.

TCAD Framework for HCD Kinetics in Low V<inf>D</inf>Devices Spanning Full V<inf>G</inf>/V<inf>D</inf>Space
Uma Sharma, Meng Duan, Himanshu Diwakar, Karansingh Thakor, Hiu Yung Wong, Steve Motzny, Denis Dolgos, and Souvik Mahapatra
Institute of Electrical and Electronics Engineers (IEEE)
The time kinetics of hot carrier degradation (HCD) is modeled using a reaction diffusion drift (RDD) framework. It is incorporated into Sentaurus Device TCAD and validated using conduction mode HCD data in n- and p-channel MOSFETs and FinFETs. RDD-enabled TCAD calculates carrier-energy-initiated generation of interface traps (<inline-formula> <tex-math notation="LaTeX">$\\Delta {N}_{\\text {IT}}$ </tex-math></inline-formula>) and the impact of the resulting localized charges on device parametric drift. HCD at various gate (<inline-formula> <tex-math notation="LaTeX">${V}_{\\text {G}}$ </tex-math></inline-formula>) and drain (<inline-formula> <tex-math notation="LaTeX">${V}_{\\text {D}}$ </tex-math></inline-formula>) biases spanning various modes (<inline-formula> <tex-math notation="LaTeX">${V}_{\\text {G}}\\le $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$>{V}_{\\text {D}}$ </tex-math></inline-formula>) are simulated for low stress <inline-formula> <tex-math notation="LaTeX">${V}_{\\text {D}}$ </tex-math></inline-formula> (< 3 V). The self-heating (SH)-effect-induced temperature (<inline-formula> <tex-math notation="LaTeX">$\\textit {T}$ </tex-math></inline-formula>) increase is invoked for FinFETs. Data from various experiments are analyzed and a wide range of power-law time kinetics slope (<inline-formula> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula>) is explained.

Study of Gate Misalignment Effects in Single-Material Double-Gate (SMDG) MOSFET Considering Source and Drain Lateral Gaussian Doping Profile
Himanshu Diwakar, Suvendu Nayak, and Rohit Kumar
IEEE
Un-intentional misalignment in the gate due to fabrication leads to undesirable device performances. In this paper, effect of gate misalignment has been presented in single-material double-gate (SMDG) MOSFET, based on simulation. The source and drain are considered to be doped with lateral Gaussian doping profile. A simulation study is performed to analyze the gate misalignment effects on the performance. A combination of total four misalignment is simulated, the effects on surface potential, device I-V characteristics and transconductance has been studied. We consider the misalignment at drain and source side of both front and back gate. When misalignment is there both trans-conductance and drain current decreases. Misalignment from drain and source side decreases trans-conductance similarly, but for 45% misalignment in the front gate, 34.8% degradation in the drain current is observed while similar misalignment in back gate causes 57.5% degradation. For simulations 2-D simulations by ATLAS™ from Silvaco Inc. is used and surface potential profile is obtained.

Low Loss Ohmic Type Piezoelectric Actuated RF MEMS Switch Designed with PZT and ZnO
Suvendu Nayak, Jogesh Chandra Dash, and Himanshu Diwakar
IEEE
RF switch is the potential alternative to replace the conventional electronic switch in high-speed applications. In this research, the design of an ohmic type piezoelectric actuated RF switch using two different piezo material such as PZT and ZnO are carried out. The switch is designed initially with the help of mathematical modeling and the modeling results are verified in the simulation environment. The fabrication steps are also highlighted for the switch along with the return loss and insertion loss associated with it.

RECENT SCHOLAR PUBLICATIONS

A TCAD Framework for HCD in n-MOSFETs for PMIC Applications
H Diwakar, S Mahapatra
2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3 2024

A Generic Framework for MOSFET Reliability—Part II: Gate and Drain Stress—HCD
Souvik Mahapatra, Himanshu Diwakar, Karansingh Thakor, Nilotpal Choudhury ...
IEEE Transactions on Electron Devices, 12 2023

Modeling of channel hot electron degradation in n-MOSFETs
K Thakor, H Diwakar, S Mahapatra
2022 IEEE 16th International Conference on Solid-State & Integrated Circuit 2022

Modeling of classical channel hot electron degradation in n-MOSFETs using TCAD
H Diwakar, K Thakor, S Mahapatra
IEEE Transactions on Electron Devices 69 (7), 3596-3603 2022

Modeling Time and Bias Dependence of Classical HCD Mechanism (Peak I_SUB Stress) in n-MOSFETs
H Diwakar, K Thakor, S Mahapatra
2022 IEEE International Reliability Physics Symposium (IRPS), P55-1-P55-6 2022

TCAD Framework for HCD Kinetics in Low V_D Devices Spanning Full V_G/V_D Space
U Sharma, M Duan, H Diwakar, K Thakor, HY Wong, S Motzny, D Dolgos, ...
IEEE Transactions on Electron Devices 67 (11), 4749-4756 2020

Low Loss Ohmic Type Piezoelectric Actuated RF MEMS Switch Designed with PZT and ZnO
S Nayak, JC Dash, H Diwakar
2018 IEEE Electron Devices Kolkata Conference (EDKCON), 6-9 2018

Study of gate misalignment effects in single-material double-gate (SMDG) MOSFET considering source and drain lateral Gaussian doping profile
H Diwakar, S Nayak, R Kumar
2018 IEEE Electron Devices Kolkata Conference (EDKCON), 11-14 2018

MOST CITED SCHOLAR PUBLICATIONS

Modeling of classical channel hot electron degradation in n-MOSFETs using TCAD
H Diwakar, K Thakor, S Mahapatra
IEEE Transactions on Electron Devices 69 (7), 3596-3603 2022
Citations: 8

Modeling of channel hot electron degradation in n-MOSFETs
K Thakor, H Diwakar, S Mahapatra
2022 IEEE 16th International Conference on Solid-State & Integrated Circuit 2022
Citations: 1