Jagritee Talukdar

Scopus Publications

Comparative performance evaluation of nanosheet FET with novel channel designs for high-performance applications
Imon Shahriar, Jagritee Talukdar, Bibhas Manna
Micro and Nanostructures, 2026
Reliable and Efficient Logic Circuit Design Using Pocket-Engineered NCFET
Malvika, Jagritee Talukdar, Bijit Choudhuri, Kavicharan Mummaneni
Silicon, 2026
TMDC-based TFETs: Progress, potential, and pathways to energy-efficient electronics
Jagritee Talukdar, Malvika, Basab Das, Ashutosh Srivastava, Wangkheirakpam Vandana Devi, Rajan Singh
Micro and Nanostructures, 2026
Mitigating NDR for Improved RF Performance in MoS2 Ferroelectric Tunnel FET
Jagritee Talukdar, Bhaskaran Muralidharan
IEEE Transactions on Nanotechnology, 2026
The work realized a steep-slope <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathrm{MoS_{2}}$</tex-math></inline-formula> based negative capacitance-tunnel field effect transistor (NC-TMDTFET) through the incorporation of the ferroelectric layer into the gate stack. The proposed device sustained a subthreshold slope of 0.023V/decade and 0.018V/decade in forward and reverse sweep respectively and an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathrm{ON/OFF}$</tex-math></inline-formula> current ratio of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$10^{12}$</tex-math></inline-formula>. The work investigates the effect of the ferroelectric layer on input and output characteristics. In the subsequent observation, it was noted that as the drain voltage increases, there is a decrease in current, indicating the presence of negative differential resistance (NDR) within the proposed device. However, mitigation of such effect in TMD based NC-TFET has not yet been introduced. Hence, to address the NDR issue hetero-dielectric BOX (H-BOX) is introduced which directly influences the gate-to-drain capacitance of the device. We report a 56.71% reduction in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$C_{GD}$</tex-math></inline-formula>, a 15.83% improvement in intrinsic delay, and a corresponding 48.95% improvement in cutoff frequency due to the introduction of H-BOX resulting enhancement in device speed. These improvements demonstrate that H-BOX integration effectively enhances key parameters making it a viable solution for analog applications that require high performance and low power consumption.
Design and Temperature-Sensitive Behavior of a Gate-Underlapped Negative Capacitance MoS2 TFET for Low-Power Applications
Malvika, Jagritee Talukdar, Bhaskaran Muralidharan
10th IEEE Electron Devices Technology and Manufacturing Conference Emerging Semiconductor Devices and Manufacturing Technologies Edtm 2026, 2026
The incessant quest for shrinking transistor sizes has been responsible for unprecedented issues in modern CMOS technology, mostly owing to increased power consumption, thermal stress, and reliability problems. Tunnel Field-Effect Transistors (TFETs) have, however, been identified as a possible alternative to conventional MOSFETs owing to their ability to attain subthreshold swing (SS) levels less than the fundamental limit of 60 mV/decade. Additionally, the inclusion of transitionmetal dichalcogenides (TMDCs) such as Molybdenum Disulfide (MoS<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>) in TFETs offers unique prospects as a result of their best electrical, thermal, and optical characteristics. This work describes the design and investigation of a new Gate-Underlap Lightly Doped Drain (LDD) double gate Negative Capacitance TFET (GU-LDD-DG-NC-TFET) with raised drain employing MoS<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> as the channel material. The device proposed utilizes ferroelectric materials for SS enhancement, LDD structures to control short channels more, and S/D underlap areas for leakage current reduction. In addition, the device performance is analyzed under different thermal conditions to confirm its suitability for ultra-low-power applications, and hence it is a potential candidate for future RF/CMOS and IoT technologies.
Temperature tolerance and sensitivity analysis of vertical TFET based biosensor under the influence of interface trap charges
Vandana Devi Wangkheirakpam, Jagritee Talukdar
Micro and Nanostructures, 2025
Analytical modeling and TCAD simulation of surface potential and drain current for pocket doped negative capacitance field-effect transistor
Malvika, Jagritee Talukdar, Bijit Choudhuri, Kavicharan Mummaneni
Physica Scripta, 2025
In this work, a 2D analytical model for a Highly Doped Double Pocket Double Gate NCFET (HDDP-DG-NCFET) device has been developed. The proposed device HDDP-DG-NCFET comprises double gate, ferroelectric material, highly doped pockets at the edge of source-channel and drain-channel junction and spacers. The double gate and the silicon doped HfO2 ferroelectric material provides better electrostatic control over the channel and improved subthreshold swing, respectively. The body is made more confined against the junction walls by incorporating a thin, highly doped region of a similar doping, which serves to reduce the extent of depletion regions that further increases the channel length for gate control and reduces short channel effects. Further, the device consists of spacers which increase the ON current. The HDDP-DG-NCFET provides I ON , I OFF , I ON /I OFF ratio and SS of 2.1 × 10−3 A/μm, 2.65 × 10−13 A/μm, 0.79 × 1010 and 25.5 mV/decade, respectively. The framework of the model is derived from the Poisson’s equation, LK equation and solved utilizing appropriate boundary conditions. The developed model is projected for several device variables, including electric field, surface potential and drain current. Afterward, to verify the model’s accuracy, Sentaurus TCAD has been utilized for device simulation, and a good agreement with 85–95% precision is witnessed. The comprehensive and structured analysis of device is provided by examining variations in dimensions of device, ferroelectric material and oxide materials. The presented analysis shows that, the proposed HDDP-DG-NCFET device has significant potential for low power applications.
Exploring the Potential of Tunnel Field-Effect Transistors in Biomedical Devices: A Comprehensive Survey
Swagata Devi, Jagritee Talukdar, Naushad Manzoor Laskar, Sagarika Choudhury
IETE Journal of Research, 2025
Implantable medical devices have revolutionized healthcare by providing continuous monitoring and therapeutic interventions within the human body. The overall performance of these devices is heavily dependent on the effectiveness and efficiency of integrated electronic components, such as transistors. This survey explores the growing utilization of Tunnel Field-Effect Transistors (TFETs) in implantable devices, shedding light on their advantages and challenges in this specific application domain. TFETs, characterized by their unique tunnelling mechanism, offer several advantages that make them well suited for implantable devices. Their low-power consumption, reduced leakage current, and improved subthreshold swing make them ideal for energy-efficient, long-lasting operation within the constrained power budgets of implantable devices. Furthermore, TFETs exhibit excellent performance at low supply voltages, ensuring minimal tissue damage and heat generation. This survey also addresses the challenges associated with TFETs in implantable devices, including fabrication complexities, variability, and compatibility with existing technologies. It highlights recent advancements in TFET technology that address these concerns, such as improved material choices and manufacturing techniques. As technology continues to advance, TFETs are poised to play a pivotal role in improving the overall efficiency and reliability of life-saving technologies and medical devices. Overall, this survey provides valuable insights into the current state and future prospects of TFETs in implantable devices, guiding researchers and engineers in harnessing their potential for the benefit of healthcare and patient well-being.
Unleashing the Potential of Negative Capacitance Field Effect Transistors: A Paradigm Shift in Low-Power Electronics
Malvika, Jagritee Talukdar, Bijit Choudhuri, Kavicharan Mummaneni
Handbook of Advanced Semiconductor Field Effect Transistors, 2025
The relentless drive towards miniaturization in micro- and nanoelectronic systems has underscored the criticality of power consumption management. This pursuit encounters a formidable obstacle known as Boltzmann tyranny, wherein the generation of a significant drain current necessitates a minimum gate voltage of approximately 60 mV. This imposes a substantial limitation on the scalability of supply voltage in Ultra-Large-Scale Integration (ULSI) circuits, hindering their ability to adapt to the diminishing dimensions of traditional transistors. In response to this pressing challenge, the negative capacitance field-effect transistor (NCFET) has emerged as a promising solution. NCFET represents a ground-breaking advancement in the field of low-power electronics, offering a promising avenue for overcoming the fundamental limitations of traditional transistor technologies. This novel transistor leverages the unique property of negative capacitance to achieve subthermal swing and enhance the performance of electronic devices, thereby enabling unprecedented reductions in power consumption. The NCFET operates based on the principle of exploiting ferroelectric materials to induce negative capacitance, resulting in an intrinsic voltage amplification effect. This breakthrough technology effectively addresses the power-efficiency challenges faced by conventional transistors, allowing for the realization of ultralow-power electronic devices without compromising performance metrics. This chapter explores the underlying physics, engineering aspects, design, and simulation methodology of NCFET, highlighting their probable application in circuits. The NCFET has emerged as a transformative technology, promising a paradigm shift towards ultralow-power electronics, highlighting their significance in the ongoing quest for energy-efficient and high-performance electronic devices.
Tunnel Field Effect Transistors: Harnessing Light Sensitivity for Optical Sensing
Jagritee Talukdar, Malvika, Basab Das, Kavicharan Mummaneni
Handbook of Advanced Semiconductor Field Effect Transistors, 2025
Tunnel field effect transistors (TFET), characterized by gated p-i-n structures, are renowned for their rapid switching capabilities owing to their band-to-band tunneling mechanism, which makes them capable of achieving a low subthreshold swing (SS). Extensively researched as potential substitutes for MOSFETs, particularly for low-voltage and low-power applications. The numerous benefits of TFETs extend their utility across sensing applications including biosensing, image sensors, and temperature sensing. This study primarily focuses on exploring TFETs’ optical sensitivity. Optical sensing has wide-ranging applications in medical diagnostics, chemical-mixing configurations, military equipment, and energy harvesting. Recently, optical sensors based on FETs have garnered significant attention owing to their compatibility with integrated circuits in low-power applications. In this study, we explore an extended source double-gate TFET (ES-DGTFET) photosensor. The device facilitates lateral tunneling as well as vertical band-to-band tunneling owing to the extended source. As a result, the device was capable of achieving a high ON current and low SS. The upper gate of the ES-DGTFET was replaced by an optical gate that was responsible for the generation of photovoltage upon excitation by light of a specific wavelength and intensity. To investigate the performance of the TFET photosensor, different parameters, such as photocurrent, response, and quantum efficiency, were observed for the proposed device. The photosensor is capable of achieving a current of 5.08×10 −6 A/μm, responsivity of approximately 10 5 , and quantum efficiency of more than 50% for an incident light of wavelength 450 nm and intensity of 0.8 W/cm 2 .
Temperature Sensitivity and Reliability in Asymmetric 3D GAA Nanowire NCFETs: Beyond Room Temperature for Next-Gen Nanoelectronics
Malvika, Ashutosh Srivastava, Divya Srivastava, Prabhat Singh, Rajan Singh, Jagritee Talukdar
Proceedings of 1st IEEE Uttar Pradesh Section Women in Engineering International Conference on Electrical Electronics and Computer Engineering Upwiecon 2025, 2025
Emerging Transition Metal Dichalcogenides (TMDCs) in Semiconductor Design A Path to Next-Generation Electronics
Classical to Quantum Transport in Multi Dimensional Field Effect Transistors, 2025
Sensitivity and reliability assessment of pocket doped NCFET based dielectrically modulated biosensor considering steric hindrance effects
Malvika, Jagritee Talukdar, Bijit Choudhuri, Kavicharan Mummaneni
Physica Scripta, 2024
Source engineered TFET for digital inverters application
Jagritee Talukdar, Malvika, Basab Das, Gopal Rawat, Kavicharan Mummaneni
Physica Scripta, 2024
Performance Analysis of Optically Gated MoS2Photosensor for Visible Light Detection
Jagritee Talukdar, Bhaskaran Muralidharan
IEEE Sensors Journal, 2024
Analysing the Sensitivity of a Photosensor Based on MoS2 TFET for Visible Light Detection
Jagritee Talukdar, Bhaskaran Muralidharan
Proceedings of the International Conference on Numerical Simulation of Optoelectronic Devices Nusod, 2024
Performance improvement of trap charge infused MoS2 based TFET photosensor by dielectric engineering.
Jagritee Talukdar, Bhaskaran Muralidharan
IEEE Electron Devices Technology and Manufacturing Conference Strengthening the Globalization in Semiconductors Edtm 2024, 2024
A Simulation Study of the Effect of Trap Charges and Temperature on Performance of Dual Metal Strip Double Gate TFET
Korra Nikhil, K Murali Chandra Babu, Jagritee Talukdar, Ekta Goel
Silicon, 2024
Analysis of noise behavior and reliability of pocket doped negative capacitance FET under the impact of trap charges and temperature
Malvika, Jagritee Talukdar, Bijit Choudhuri, Kavicharan Mummaneni
Microelectronics Reliability, 2024
Exploration of Graphene as Emerging 2D Material and Its Applications: A Review
Malvika, Jagritee Talukdar, Bijit Choudhuri, Gopal Rawat, Kavicharan Mummaneni
Lecture Notes in Networks and Systems, 2024
Design and Implementation of an Optimized High-Speed Vedic-Based Squarer Circuit Using Reversible Logic Gates
Saurabh Halder, Mihir Lal Saha, Malvika, Jagritee Talukdar, Kavicharan Mummaneni
Lecture Notes in Electrical Engineering, 2024
Comparative Analysis of Noise Behavior of Highly Doped Double Pocket Double-Gate and Single-Gate Negative Capacitance FET
Malvika, Jagritee Talukdar, Vivek Kumar, Bijit Choudhuri, Kavicharan Mummaneni
Journal of Electronic Materials, 2023
Highly sensitivity Non-Uniform Tunnel FET based biosensor using source engineering
Jagritee Talukdar, Gopal Rawat, Kavicharan Mummaneni
Materials Science and Engineering B, 2023
Design and Analysis of Non-uniform Body with Dual Material FET-Based Digital Inverter
Jagritee Talukdar, Kavicharan Mummaneni
Lecture Notes in Electrical Engineering, 2023
A Reliability Study of Non-uniform Si TFET with Dual Material Source: Impact of Interface Trap Charges and Temperature
Jagritee Talukdar, Kavicharan Mummaneni
Silicon, 2022
Source pocket-engineered hetero-gate dielectric SOI Tunnel FET with improved performance
Vanshaj Sharma, Sanjay Kumar, Jagritee Talukdar, Kavicharan Mummaneni, Gopal Rawat
Materials Science in Semiconductor Processing, 2022
Analytical modeling and TCAD simulation for subthreshold characteristics of asymmetric Tunnel FET
Jagritee Talukdar, Gopal Rawat, Kavicharan Mummaneni
Materials Science in Semiconductor Processing, 2022
Noise behavior and reliability analysis of non-uniform body tunnel FET with dual material source
Jagritee Talukdar, Gopal Rawat, Kavicharan Mummaneni
Microelectronics Reliability, 2022
Flicker Noise Analysis of Non-uniform Body TFET with Dual Material Source (NUTFET-DMS)
Jagritee Talukdar, G. Amarnath, Kavicharan Mummaneni
Lecture Notes in Electrical Engineering, 2022
Sensitivity analysis of Non-uniform TFET with dual material source-based biosensor
Jagritee Talukdar, Malvika Malvika, Basab Das, Kavicharan Mummaneni
Proceedings 2022 IEEE International Symposium on Smart Electronic Systems Ises 2022, 2022
A simulation study of the effect of ferroelectric thickness and oxide variation on the performance of Highly Doped Double Pocket Double Gate NCFET based inverter
Malvika Malvika, Jagritee Talukdar, Bijit Choudhuri, Kavicharan Mummaneni
Proceedings 2022 IEEE International Symposium on Smart Electronic Systems Ises 2022, 2022
Radix-10 Multiplier Implementation with Carry Skip Adder Using Verilog
M. Shashikumar, Bhaskar Jyoti Das, Jagritee Talukdar, Kavicharan Mummaneni
Lecture Notes in Electrical Engineering, 2022
Dielectrically Modulated Single and Double Gate Tunnel FET Based Biosensors for Enhanced Sensitivity
Jagritee Talukdar, Gopal Rawat, Kavicharan Mummaneni
IEEE Sensors Journal, 2021
Low Frequency Noise Analysis of Single Gate Extended Source Tunnel FET
Jagritee Talukdar, Gopal Rawat, Kunal Singh, Kavicharan Mummaneni
Silicon, 2021
Impact of temperature and different types of trap charges on noise behavior of Non-uniform Body with Dual Material Source TFET (NUTFET-DMS)
Jagritee Talukdar, Kavicharan Mummaneni
Proceedings of 4th International Conference on 2021 Devices for Integrated Circuit Devic 2021, 2021
Impact of temperature counting the effect of back gate bias on the performance of extended source tunnel FET (ESTFET) with δp+ SiGe pocket layer
Jagritee Talukdar, Bijit Choudhuri, Kavicharan Mummaneni
Applied Physics A Materials Science and Processing, 2021
Device physics based analytical modeling for electrical characteristics of single gate extended source tunnel FET (SG-ESTFET)
Jagritee Talukdar, Gopal Rawat, Bijit Choudhuri, Kunal Singh, Kavicharan Mummaneni
Superlattices and Microstructures, 2020
A Novel Extended Source TFET with δp+- SiGe Layer
Jagritee Talukdar, Gopal Rawat, Kavicharan Mummaneni
Silicon, 2020
Estimation of frequency and amplitude of ring oscillator built using current sources
Abir J. Mondal, J. Talukdar, Bidyut K. Bhattacharyya
Ain Shams Engineering Journal, 2020
Noise Behavior of SG-ESTFET with Various Interface Trap Charges
Jagritee Talukdar, Kavicharan Mummaneni
2020 International Conference on Computational Performance Evaluation Compe 2020, 2020
Comparative Analysis of the Effects of Trap Charges on Single- and Double-Gate Extended-Source Tunnel FET with δp+ SiGe Pocket Layer
Jagritee Talukdar, Gopal Rawat, Kunal Singh, Kavicharan Mummaneni
Journal of Electronic Materials, 2020
Variation aware design of controlled voltage swing ring oscillator
Abir J. Mondal, J. Talukdar, Bidyut K. Bhattacharyya
International Journal of Electronics, 2020
A non-uniform silicon TFET design with dual-material source and compressed drain
Jagritee Talukdar, Kavicharan Mummaneni
Applied Physics A Materials Science and Processing, 2020
An improved TIQ comparator based 3-bit flash ADC
Jagritee Talukdar, Basab Das
2017 1st International Conference on Electronics Materials Engineering and Nano Technology Iementech 2017, 2017

RECENT SCHOLAR PUBLICATIONS

Mitigating NDR for Improved RF Performance in Ferroelectric Tunnel FET
J Talukdar, B Muralidharan
IEEE Transactions on Nanotechnology , 2026
2026
Comparative performance evaluation of nanosheet FET with novel channel designs for high-performance applications
I Shahriar, J Talukdar, B Manna
Micro and Nanostructures, 208642 , 2026
2026
Design and Temperature-Sensitive Behavior of a Gate-Underlapped Negative Capacitance MoS 2 TFET for Low-Power Applications
J Talukdar, B Muralidharan
2026 10th IEEE Electron Devices Technology & Manufacturing Conference (EDTM … , 2026
2026
Flicker Noise Estimation of Pocket Doped NCFET in Existence of Interface Traps and Temperature
M Malvika, J Talukdar, B Choudhuri, K Mummaneni
2026 International Conference on Intelligent Processing, Hardware … , 2026
2026
Trap-Induced Transport and Electrostatic Effects in Gate-Underlapped MoS 2 Negative Capacitance TFET
P Singh, B Manna, J Talukdar
2026 International Conference on Intelligent Processing, Hardware … , 2026
2026
Reliable and Efficient Logic Circuit Design Using Pocket-Engineered NCFET
Malvika, J Talukdar, B Choudhuri, K Mummaneni
Silicon, 1-12 , 2026
2026
Unleashing the Potential of Negative Capacitance Field Effect Transistors
J Talukdar, B Choudhuri, K Mummaneni
Wiley Semiconductors , 2026
2026
Unleashing the Potential of Negative Capacitance Field Effect Transistors: A Paradigm Shift in Low‐Power Electronics
Malvika, J Talukdar, B Choudhuri, K Mummaneni
Handbook of Advanced Semiconductor Field Effect Transistorss, 73-88 , 2025
2025
Tunnel Field Effect Transistors: Harnessing Light Sensitivity for Optical Sensing
J Talukdar, Malvika, B Das, K Mummaneni
Handbook of Advanced Semiconductor Field Effect Transistorss, 169-182 , 2025
2025
TMDC-based TFETs: Progress, potential, and pathways to energy-efficient electronics
J Talukdar, B Das, A Srivastava, WV Devi, R Singh
Micro and Nanostructures, 208460 , 2025
2025
Temperature Sensitivity and Reliability in Asymmetric 3D GAA Nanowire NCFETs: Beyond Room Temperature for Next-Gen Nanoelectronics
A Srivastava, D Srivastava, P Singh, R Singh, J Talukdar
2025 1st IEEE Uttar Pradesh Section Women in Engineering International … , 2025
2025
Emerging Transition Metal Dichalcogenides (TMDCs) in Semiconductor Design: A Path to Next-Generation Electronics
A Srivastava, J Talukdar, R Singh, P Singh, JV Suman
Classical to Quantum Transport in Multi-Dimensional Field Effect Transistors … , 2025
2025
Temperature tolerance and sensitivity analysis of vertical TFET based biosensor under the influence of interface trap charges
VD Wangkheirakpam, J Talukdar
Micro and Nanostructures 205, 208185 , 2025
2025
Analytical modeling and TCAD simulation of surface potential and drain current for pocket doped negative capacitance field-effect transistor
Malvika, J Talukdar, B Choudhuri, K Mummaneni
Physica Scripta 100 (3), 035013 , 2025
2025
Citations: 2
Exploring the Potential of Tunnel Field-Effect Transistors in Biomedical Devices: A Comprehensive Survey
S Devi, J Talukdar, NM Laskar, S Choudhury
IETE Journal of Research 71 (1), 247-258 , 2025
2025
Citations: 2
Sensitivity and reliability assessment of pocket doped NCFET based dielectrically modulated biosensor considering steric hindrance effects
Malvika, J Talukdar, B Choudhuri, K Mummaneni
Physica Scripta 99 (10), 105021 , 2024
2024
Citations: 2
Analysing the Sensitivity of a Photosensor Based on MoS 2 TFET for Visible Light Detection
J Talukdar, B Muralidharan
2024 International Conference on Numerical Simulation of Optoelectronic … , 2024
2024
Citations: 1
Performance Analysis of Optically Gated MoS 2 Photosensor for Visible Light Detection
J Talukdar, B Muralidharan
IEEE Sensors Journal 24 (15), 23810-23817 , 2024
2024
Citations: 6
Source engineered TFET for digital inverters application
J Talukdar, Malvika, B Das, G Rawat, K Mummaneni
Physica Scripta 99 (4), 045026 , 2024
2024
Citations: 2
Performance improvement of trap charge infused MoS 2 based TFET photosensor by dielectric engineering.
J Talukdar, B Muralidharan
2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3 , 2024
2024
Citations: 1

MOST CITED SCHOLAR PUBLICATIONS

Dielectrically modulated single and double gate tunnel FET based biosensors for enhanced sensitivity
J Talukdar, G Rawat, K Mummaneni
IEEE Sensors Journal 21 (23), 26566-26573 , 2021
2021
Citations: 86
A novel extended source TFET with δp+-SiGe layer
J Talukdar, G Rawat, K Mummaneni
Silicon 12 (10), 2273-2281 , 2020
2020
Citations: 71
A non-uniform silicon TFET design with dual-material source and compressed drain
J Talukdar, K Mummaneni
Applied Physics. A, Materials Science & Processing 126 (1), 81 , 2020
2020
Citations: 51
Comparative Analysis of the Effects of Trap Charges on Single-and Double-Gate Extended-Source Tunnel FET with dp SiGe Pocket Layer
J Talukdar, G Rawat, K Singh, K Mummaneni
2020
Citations: 35
Low frequency noise analysis of single gate extended source tunnel FET
J Talukdar, G Rawat, K Singh, K Mummaneni
Silicon 13 (11), 3971-3980 , 2021
2021
Citations: 29
Source pocket-engineered hetero-gate dielectric SOI Tunnel FET with improved performance
V Sharma, S Kumar, J Talukdar, K Mummaneni, G Rawat
Materials Science in Semiconductor Processing 143, 106541 , 2022
2022
Citations: 24
Highly sensitivity Non-Uniform Tunnel FET based biosensor using source engineering
J Talukdar, G Rawat, K Mummaneni
Materials Science and Engineering: B 293, 116455 , 2023
2023
Citations: 21
Device physics based analytical modeling for electrical characteristics of single gate extended source tunnel FET (SG-ESTFET)
J Talukdar, G Rawat, B Choudhuri, K Singh, K Mummaneni
Superlattices and Microstructures 148, 106725 , 2020
2020
Citations: 21
Estimation of frequency and amplitude of ring oscillator built using current sources
AJ Mondal, J Talukdar, BK Bhattacharyya
Ain Shams Engineering Journal 11 (3), 677-686 , 2020
2020
Citations: 17
Analytical modeling and TCAD simulation for subthreshold characteristics of asymmetric tunnel FET
J Talukdar, G Rawat, K Mummaneni
Materials Science in Semiconductor Processing 142, 106482 , 2022
2022
Citations: 9
Impact of temperature counting the effect of back gate bias on the performance of extended source tunnel FET (ESTFET) with δp+ SiGe pocket layer
J Talukdar, B Choudhuri, K Mummaneni
Applied Physics. A, Materials Science & Processing 127 (1), 24 , 2021
2021
Citations: 9
A simulation study of the effect of trap charges and temperature on performance of dual metal strip double gate TFET
K Nikhil, KMC Babu, J Talukdar, E Goel
Silicon 16 (2), 525-534 , 2024
2024
Citations: 8
Noise behavior and reliability analysis of non-uniform body tunnel FET with dual material source
J Talukdar, G Rawat, K Mummaneni
Microelectronics Reliability 131, 114510 , 2022
2022
Citations: 8
Performance Analysis of Optically Gated MoS 2 Photosensor for Visible Light Detection
J Talukdar, B Muralidharan
IEEE Sensors Journal 24 (15), 23810-23817 , 2024
2024
Citations: 6
Comparative analysis of noise behavior of highly doped double pocket double-gate and single-gate negative capacitance FET
Malvika, J Talukdar, V Kumar, B Choudhuri, K Mummaneni
Journal of Electronic Materials 52 (9), 6203-6215 , 2023
2023
Citations: 5
A reliability study of non-uniform Si TFET with dual material source: impact of interface trap charges and temperature
J Talukdar, K Mummaneni
Silicon 14 (9), 4515-4521 , 2022
2022
Citations: 5
A novel extended source TFET with δp+− SiGe layer. Silicon 12: 2273–2281
J Talukdar, G Rawat, K Mummaneni
2020
Citations: 5
Analysis of noise behavior and reliability of pocket doped negative capacitance FET under the impact of trap charges and temperature
J Talukdar, B Choudhuri, K Mummaneni
Microelectronics Reliability 152, 115301 , 2024
2024
Citations: 4
An improved TIQ comparator based 3-bit flash ADC
J Talukdar, B Das
2017 1st International Conference on Electronics, Materials Engineering and … , 2017
2017
Citations: 4
Sensitivity analysis of Non-uniform TFET with dual material source-based biosensor
J Talukdar, M Malvika, B Das, K Mummaneni
2022 IEEE International Symposium on Smart Electronic Systems (iSES), 597-600 , 2022
2022
Citations: 3

Jagritee Talukdar

RESEARCH, TEACHING, or OTHER INTERESTS

Scopus Publications

RECENT SCHOLAR PUBLICATIONS

MOST CITED SCHOLAR PUBLICATIONS