MALATHI L

Verified @gmail.com

Assistant Professor, Electronics and Communication Engineering
SRI RAMAKRISHNA INSTITUTE OF TECHNOLOGY

MALATHI L


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https://researchid.co/malathiraj
Dr. L. Malathi, received her Ph.D. degree in Applied Electronics from Anna University, Chennai in the year 2023. She received her M.E. degree in Applied Electronics from Anna University, Chennai in the year 2008. She received her B.E. degree in Electronics and Communication Engineering from Anna University, Chennai in the year 2005. Doing research work in the areas of signal processing, VLSI and image processing. Currently she is working as Assistant Professor in ECE Department at Sri Ramakrishna Institute of Technology, Coimbatore. She is having 13 years of teaching experience. She has published & presented papers in various National and International Conferences & Journals.

EDUCATION

Master of Engineering

RESEARCH INTERESTS

VLSI, DSP
6

Scopus Publications

52

Scholar Citations

4

Scholar h-index

2

Scholar i10-index

Scopus Publications

  • Efficient FPGA Accelerator for ECG Signal Classification Using dCViTrN and Optimized Booth Multiplier
    L. Malathi
    Transactions on Emerging Telecommunications Technologies, 2026
    ECG signal classification is important for the early detection of cardiovascular disorders (CVDs). The current methods have been struggling with the nonlinear complexity of ECG signals, making them inefficient for real‐time diagnostic analysis. Thus, this paper proposes a new FPGA‐based deep convolutional vision transformer network (dCViTrN) (FPGA‐dCViTrN) accelerator to detect different types of arrhythmias. While performing the ECG signal classification process, an unsigned divide, and conquer‐based look‐up‐table (LUT) oriented booth multiplier (UDC‐LUT‐BM) is used to perform complex mathematical operations of dCViTrN, like multiplication, for minimizing the complexity. Two publicly available datasets, specifically the PTB‐XL and MIT‐BIH arrhythmia, are used for experimentation. Furthermore, a variety of performance indicators, including accuracy, recall, precision, and F1‐score, are utilized to evaluate the deep learning accelerator. In addition, delay, resource utilization, and power consumption are used to assess the hardware complexity. The findings show that the FPGA‐dCViTrN design delivers 99.25% and 99.7% classification accuracy on the MIT‐BIH and PTB‐XL datasets. Overall, this research provides a robust, high‐accuracy deep‐learning model strengthened by an optimized FPGA architecture, allowing for enhanced, real time ECG classification and assessment in medical diagnostics.
  • Ad-MNet with FConv: FPGA-enabled advanced MobileNet model with fast convolution accelerator for image resolution and quality enhancement
    L. Malathi
    Signal Processing Image Communication, 2026
  • FPGA design of FFT based intelligent accelerator with optimized Wallace tree multiplier for image super resolution and quality enhancement
    L. Malathi, A. Bharathi, A.N. Jayanthi
    Biomedical Signal Processing and Control, 2024
  • RDO-WT: optimised Wallace Tree multiplier based FIR filter for signal processing applications
    L. Malathi, A. Bharathi, A. N. Jayanthi
    International Journal of Electronics, 2022
    Digital Signal Processing (DSP) and communication applications utilise a Finite Impulse Response (FIR) filter which is key component for digital communication. Moreover, quality of signal is enhanced by FIR filter which is mostly employed by filtering applications. The execution speed of the FIR is determined by multiplier’s performance. Hardware resource utilisation and speed-up operations are some of the issues found in existing methods which are occurred due to a critical path in incomplete products. So, this can be improved by the proposed optimisation algorithm based multiplier. This research establishes the execution of FIR Filter design using Red Deer Optimisation (RDO) based Wallace Tree (WT) multiplier. By using the optimised WT multiplier, FIR filter is simulated to examine the area, delay, power and frequency for different tap FIR filter. Moreover, FIR filter with optimised WT is introduced to perform signal denoising application. Proposed multiplier design is simulated using Xilinx tool. Filtering simulation is done by using the publicly available database named as MIT-BIH database and the noise removal process is simulated using Matlab tool. The FIR filter designed with proposed multiplier provides delay around 1.373 ns and consumes 0.143 W as total power which is lesser than the existing methods.
  • FPGA Implementation of Adaptive NMLS Algorithm: Timbre Based Filtering from Multiple Harmonics using FIR Filters
    L. Malathi, A. Bharathi, A.N. Jayanthi, Narmatha C
    Proceedings of 2022 2nd International Conference on Computing and Information Technology Iccit 2022, 2022
    Technique which is used to produce various modulated sounds with different tones. The two methods are available to achieve this i.e., Additive and Subtractive Synthesis. That can be done either composition based or by filter the analyzed harmonics from the complex waves. First is based on additive and later one is based on subtractive synthesis. The modulation of the effect in sound can be alter by using filters, equalizers. The role of harmonic is in music, physics, acoustics, e-power transmission, radio technologies etc., The Harmonic is a form of repletion of signals with various power variations with integer multiples. The actual signal is first order harmonic and the following with that is called second order, third order and higher order and so on. Recursive Least Square (RLS) is basically an adaptive based algorithm. It is used to find the channel coefficients recursively which limit the weighted, straight, least square expense work with respect to the input. RLS algorithm is having best approach than other algorithm like LMS (Least Mean Square Algorithm), NLMS (Normalized Least Mean Square Algorithm), Affine Projection Algorithm (APA). APA is the advanced version of NLMS with improved convergence rate. RLS algorithm-based filters are effectively used in Bio Medical Applications, Smart Antenna in Mobile Communications, SoC Estimation, Signal Analysis etc.
  • Wearable Child safety System
    A N Jayanthi, L. Malathi, S. Munaf, A. Bharathi
    Iop Conference Series Materials Science and Engineering, 2020
    The paper focuses on a smart wearable device used for children. The main benefit of this wearable compared to other wearable is that it can be used in any of smart mobile phones and does not need a very costly mobile phone and not a highly technical human. The main idea of this wearable safety system is to aid the parents in finding their child very easily. In the current scenario, there are lot of wearable that monitors the routine behavior and activities of children and also help to find the child using Wireless Fidelity (Wi-Fi) and Bluetooth services that are available on the device. But both of them seems to be an unsecured communication in between the parent and the child. Therefore, the objective of this paper is SMS (Short message service) text enabled link in between the child’s wearable and the respective parent. The main idea for achieving this is Global System of Mobile Communication (GSM). The parent has to send a text message in the form of SMS using words like “Temperature”, “SOS”, “Location”, “Buzz” etc., to the wearable system. The wearable device sends an acknowledgement in the form of a text showing the location of the child and will provide the atmospheric temperature, so that the parents can have a track if the temperature does not suit the child. The next measure that can be taken is by using a SOS Light that is bright. Distress alarm buzzer present on the wearable device can also be activated by the parents through SMS text to display the SOS signal very clearly and rings an alarm which the nearby public can immediately react to the safety of the child till the parents come or they can try to reach he parents and assist in locating the child.

RECENT SCHOLAR PUBLICATIONS

  • Efficient FPGA Accelerator for ECG Signal Classification Using dCViTrN and Optimized Booth Multiplier
    L Malathi
    Transactions on Emerging Telecommunications Technologies 37 (4), e70410 , 2026
    2026
  • Ad-MNet with FConv: FPGA-Enabled Advanced MobileNet Model with Fast Convolution Accelerator for Image Resolution and Quality Enhancement
    L Malathi
    Signal Processing: Image Communication, 117433 , 2025
    2025
  • FPGA design of FFT based intelligent accelerator with optimized Wallace tree multiplier for image super resolution and quality enhancement
    L Malathi, A Bharathi, AN Jayanthi
    Biomedical Signal Processing and Control 88, 105599 , 2024
    2024
    Citations: 19
  • RDO-WT: optimised Wallace Tree multiplier based FIR filter for signal processing applications
    L Malathi, A Bharathi, AN Jayanthi
    International Journal of Electronics 109 (10), 1759-1780 , 2022
    2022
    Citations: 8
  • FPGA Implementation of Adaptive NMLS Algorithm: Timbre Based Filtering from Multiple Harmonics using FIR Filters
    L Malathi, A Bharathi, AN Jayanthi
    2022 2nd International Conference on Computing and Information Technology … , 2022
    2022
    Citations: 1
  • Wearable child safety system
    AN Jayanthi, L Malathi, S Munaf, A Bharathi
    IOP Conference Series: Materials Science and Engineering 932 (1), 012088 , 2020
    2020
    Citations: 5
  • FPGA Implementation in Robust FFT Architecture for Signal Processing Applications
    L.Malathi, A.Bharathi, A.N.Jayanthi
    International Journal of Innovative Technology and Exploring Engineering … , 2020
    2020
  • FPGA Implementation of Area Efficient CMOS Multiplier using Fast Kogge Stone Look Ahead Logarithmic Adder
    L . Malathi, Dr. A. Bharathi, Dr. A. N. Jayanthi
    International Journal of Recent Technology and Engineering (IJRTE), 8 (4) , 2019
    2019
  • REVIEW ON FAST COMPLEX MULTIPLICATION ALGORITHMS AND IMPLEMENTATION
    DANJ L. Malathi, Dr. A. Bharathi
    INTERNATIONAL JOURNAL OF CURRENT ENGINEERING AND SCIENTIFIC RESEARCH (IJCESR … , 2019
    2019
    Citations: 4
  • Smart aquaculture fish feeding and water quality monitoring
    L Malathi, B Harish, N Harishankar, K Manigandan, TKG Ram
    Proceedings of International Conference. Coimbatore: Coimabatore Institute … , 2018
    2018
    Citations: 1
  • Design of Fast Integer Pipelined Multipliers for CMOS 64-bit Synchronous and Asynchronous Logic with Adaptable Latency
    SM L.Malathi,Dr.A.Bharathi,Dr.A.N.Jayanthi
    International Journal of Recent and Innovation Trends in Computing and … , 2017
    2017
  • Automatic RF Alert system to Avoid Vehicle Accident and Rescue using Wireless Control Techniques
    LM S.Munaf,Dr.A.N.Jayanthi
    International Advanced Research Journal in Science, Engineering and … , 2017
    2017
  • Finger print Combination by Minutiae and Coordination Extraction for Privacy Protection
    ML Devi.P, Saranya.B
    International Journal of Latest Trends in Engineering and Technology (IJLET … , 2016
    2016
  • Computerised Collimator Positioning - Diagnostic Radiography (X- Ray)
    ML Lakshmi Priya.L
    2015
  • Design of Recoder Using FAM Technique For Efficient Multiplication
    BK L.Malathi,J.Akshaya,C.Dharani
    2015
  • Performance Analysis of Different Micro Ring Resonators based on Optical Delay Lines
    LM P.Narmadhadevi, D.Shanmuga Sundar
    International Journal of Computer Applications (IJCA) (0975 – 8887) 67 (13), 4 , 2013
    2013
    Citations: 14
  • FPGA Implementation for Recduced Memory Using Scalable Encryption Algorithm
    RK L. Malathi, L. J. Arthiha
    International Journal of Electronics Communication and Computer Engineering … , 2013
    2013
  • POWER REDUCTION OF CSLA USING CMOS
    ML Malathi.L,Bhuvana, Hemathevy, Jeevitha, Jothimani
    2013

MOST CITED SCHOLAR PUBLICATIONS

  • FPGA design of FFT based intelligent accelerator with optimized Wallace tree multiplier for image super resolution and quality enhancement
    L Malathi, A Bharathi, AN Jayanthi
    Biomedical Signal Processing and Control 88, 105599 , 2024
    2024
    Citations: 19
  • Performance Analysis of Different Micro Ring Resonators based on Optical Delay Lines
    LM P.Narmadhadevi, D.Shanmuga Sundar
    International Journal of Computer Applications (IJCA) (0975 – 8887) 67 (13), 4 , 2013
    2013
    Citations: 14
  • RDO-WT: optimised Wallace Tree multiplier based FIR filter for signal processing applications
    L Malathi, A Bharathi, AN Jayanthi
    International Journal of Electronics 109 (10), 1759-1780 , 2022
    2022
    Citations: 8
  • Wearable child safety system
    AN Jayanthi, L Malathi, S Munaf, A Bharathi
    IOP Conference Series: Materials Science and Engineering 932 (1), 012088 , 2020
    2020
    Citations: 5
  • REVIEW ON FAST COMPLEX MULTIPLICATION ALGORITHMS AND IMPLEMENTATION
    DANJ L. Malathi, Dr. A. Bharathi
    INTERNATIONAL JOURNAL OF CURRENT ENGINEERING AND SCIENTIFIC RESEARCH (IJCESR … , 2019
    2019
    Citations: 4
  • FPGA Implementation of Adaptive NMLS Algorithm: Timbre Based Filtering from Multiple Harmonics using FIR Filters
    L Malathi, A Bharathi, AN Jayanthi
    2022 2nd International Conference on Computing and Information Technology … , 2022
    2022
    Citations: 1
  • Smart aquaculture fish feeding and water quality monitoring
    L Malathi, B Harish, N Harishankar, K Manigandan, TKG Ram
    Proceedings of International Conference. Coimbatore: Coimabatore Institute … , 2018
    2018
    Citations: 1
  • Efficient FPGA Accelerator for ECG Signal Classification Using dCViTrN and Optimized Booth Multiplier
    L Malathi
    Transactions on Emerging Telecommunications Technologies 37 (4), e70410 , 2026
    2026
  • Ad-MNet with FConv: FPGA-Enabled Advanced MobileNet Model with Fast Convolution Accelerator for Image Resolution and Quality Enhancement
    L Malathi
    Signal Processing: Image Communication, 117433 , 2025
    2025
  • FPGA Implementation in Robust FFT Architecture for Signal Processing Applications
    L.Malathi, A.Bharathi, A.N.Jayanthi
    International Journal of Innovative Technology and Exploring Engineering … , 2020
    2020
  • FPGA Implementation of Area Efficient CMOS Multiplier using Fast Kogge Stone Look Ahead Logarithmic Adder
    L . Malathi, Dr. A. Bharathi, Dr. A. N. Jayanthi
    International Journal of Recent Technology and Engineering (IJRTE), 8 (4) , 2019
    2019
  • Design of Fast Integer Pipelined Multipliers for CMOS 64-bit Synchronous and Asynchronous Logic with Adaptable Latency
    SM L.Malathi,Dr.A.Bharathi,Dr.A.N.Jayanthi
    International Journal of Recent and Innovation Trends in Computing and … , 2017
    2017
  • Automatic RF Alert system to Avoid Vehicle Accident and Rescue using Wireless Control Techniques
    LM S.Munaf,Dr.A.N.Jayanthi
    International Advanced Research Journal in Science, Engineering and … , 2017
    2017
  • Finger print Combination by Minutiae and Coordination Extraction for Privacy Protection
    ML Devi.P, Saranya.B
    International Journal of Latest Trends in Engineering and Technology (IJLET … , 2016
    2016
  • Computerised Collimator Positioning - Diagnostic Radiography (X- Ray)
    ML Lakshmi Priya.L
    2015
  • Design of Recoder Using FAM Technique For Efficient Multiplication
    BK L.Malathi,J.Akshaya,C.Dharani
    2015
  • FPGA Implementation for Recduced Memory Using Scalable Encryption Algorithm
    RK L. Malathi, L. J. Arthiha
    International Journal of Electronics Communication and Computer Engineering … , 2013
    2013
  • POWER REDUCTION OF CSLA USING CMOS
    ML Malathi.L,Bhuvana, Hemathevy, Jeevitha, Jothimani
    2013