Napolean A

@aiet.org.in

Sr Assistant Professor in the Dept of ECE
Alvas Institute of Engineering and Technology

Napolean A


                  Download Compact PDF  
https://researchid.co/napolean

RESEARCH, TEACHING, or OTHER INTERESTS

Electrical and Electronic Engineering, Automotive Engineering, Electronic, Optical and Magnetic Materials, Computer Networks and Communications
28

Scopus Publications

177

Scholar Citations

8

Scholar h-index

8

Scholar i10-index

Scopus Publications

  • Securing DSP IPs: A Comprehensive Study on Logic and Structural Obfuscation Techniques
    R. Naveenkumar, N. M. Sivamangai, S. Sridevi Sathayapriya, A. Napolean
    National Academy Science Letters, 2026
  • Implementation of RSA Algorithm for Cryptography in Hardware Security
    R. Naveenkumar, N. M. Sivamangai, S. Sridevi Sathyapriya, A. Napolean
    National Academy Science Letters, 2026
  • A new approach utilizing DTCWT for feature extraction and ANN for classification to improve fingerprint recognition
    Pradeep N R, Manjunatha D V, Napolean A, Arjun Sunil Rao
    Engineering Research Express, 2025
    The authentication of biometric data using fingerprints is increasingly crucial in today’s security landscape. Despite advancements in fingerprint identification algorithms, challenges remain in matching incomplete prints. Fingerprints, known for their uniqueness and long-term durability, are widely used in biometric research, including this study. While existing literature presents successful strategies, there is still room for integrating these methods into more advanced algorithms. As technology and security demands evolve, the need for efficient, cost-effective, and reliable systems has driven researchers to develop robust algorithms. This study demonstrates a direct correlation between test and database images, with a particular focus on forensic fingerprint evidence submitted in the court of law, which must be supported by scientifically validated methods. Dual-Tree Complex Wavelet Transforms (DTCWT) is effective in capturing intricate fingerprint details by decomposing images into multiple levels while preserving directional information, making it highly suitable for fingerprint feature extraction. When combined with Artificial Neural Networks (ANNs), which excel in learning complex patterns and classifying data based on feature vectors, The identification process utilizes a combination of DTCWT for feature extraction and ANNs for classification, constructing a feature vector that forms the basis of a multiclass classifier. Using the National Institute of Standards and Technology, Special Database-4 (NIST SD-4) for evaluation, the proposed approach surpasses notable machine learning algorithms, such as K-Nearest Neighbor, Decision Tree, Random Forest, and Support Vector Machine, based on performance metrics. This approach has proven particularly effective in handling incomplete or low-quality fingerprints, addressing a major challenge in biometric authentication systems, Utilizing DTCWT and ANN in fingerprint recognition is considered a significant advancement, offering a more scalable and accurate solution for security applications, including forensic analysis and biometric identification systems. Impact Statement. The surge in information technology and the demand for heightened security have compelled researchers and scholars to seek efficient, cost-effective, accessible, and reliable methods for individual identification. Conventional fingerprint matching algorithms struggle to preserve feature information, hindering their ability to handle partial input data and perform multiple computational functions simultaneously. The adoption of Man and Machine Intelligent systems emerges as a potential solution, warranting further in-depth research. This investigation centers on deploying ANN and gauging its effectiveness using assessment metrics like F_Score, Specificity, Precision, Accuracy, and Sensitivity. It aims to compare these results with the currently prevailing machine learning algorithms and classifiers.
  • Automated Fire Detection System for Forest Areas and Public Places - Challenges and Recent Trends
    Subramanya K M, Napolean A, Prajwal N, Santhosh M, Viresh Halli
    3rd International Conference on Emerging Computation and Information Technologies Icecit 2025 Book of Abstracts, 2025
    This article provides a thorough analysis of current developments in the design and application of automated fire detection and extinguishing systems. It highlights advancements that improve accuracy and lower false alarms by focusing on sensor technology, detection algorithms, and action mechanisms. Real-time monitoring capabilities and system efficiency have been greatly enhanced by the combination of IoT and machine learning approaches. Water, foam, and chemical substances are among the fire suppression techniques whose efficacy and environmental impact are examined. There is discussion of issues with system scalability, cost, and dependability. The study also looks at new developments like Forest Areas and Public Places integration and drone-assisted fire detection. Practical insights are offered by case studies from current developments and experimental setups. The evaluation seeks to direct future investigations toward fire safety technologies that are more intelligent, flexible, and energy-efficient.
  • Design of energy-efficient hybrid STT-MTJ/CMOS-based LIM logic gates for IoT applications
    N. Aswathy, N.M. Sivamangai, A. Napolean, T. Jarin
    Measurement Sensors, 2024
    Complementary Metal Oxide Silicon (CMOS) technology faces a major concern in power dissipation due to the scale-down of technology nodes to the nanoscale. To, resolve this problem, logic-in-memory (LIM) structures are researched as a solution. A spintronics device called magnetic tunnel junction (MTJ) uses less static power than CMOS technology. To improve the energy efficiency of LIM structures, spin-transfer torque based magnetic tunnel junction (STT-MTJ) and CMOS are used to design digital circuits. In this paper, the design of hybrid AND/NAND, OR/NOR, and XOR/XNOR logic gate are done by exploring two proposed LIM designs namely LIM1 based on a pre-charge sense amplifier (PCSA) and LIM2 based on a modified version of PCSA (M-PCSA)using the Cadence simulator. This work considers the incorporation of separated transistor logic into the LIM structure to provide separate read and write paths.The results are compared in respect of delay, power, gate count and energy consumption.The proposed LIM1 and LIM2-based AND/NAND, OR/NOR and XOR/XNOR design shows 47.5%, 49.6%, 41.9% and 59.3%, 60.7%, 55.7% lower energy consumption respectively compared to the existing CMOS-based designs. This paper exhibits the design of energy efficient hybrid MTJ/CMOS structures using optimized read/write circuitry and it is appropriate for IoT applications.
  • Review on Low-Power and High-Speed Dynamic Comparators for Precise Applications
    15th International Conference on Advances in Computing Control and Telecommunication Technologies Act 2024, 2024
  • Review on Hardware Trojan Detection Techniques
    R. Naveenkumar, N. M. Sivamangai, A. Napolean, S. Sridevi Sathayapriya
    National Academy Science Letters, 2023
  • Design of INV/BUFF Logic Locking For Enhancing the Hardware Security
    R. Naveenkumar, N. M. Sivamangai, A. Napolean, S. Sridevi Sathya Priya, S. V. Ashika
    Journal of Electronic Testing Theory and Applications JETTA, 2023
  • Enhancing Encryption Security Against Cypher Attacks
    R. Naveenkumar, N. M. Sivamangai, A. Napolean, S. Sridevi Sathyapriya
    Homomorphic Encryption for Financial Cryptography Recent Inventions and Challenges, 2023
  • Importance of Logic Locking Attacks in Hardware Security
    Ashika S V, N. M. Sivamangai, R Naveenkumar, Napolean A
    Idciot 2023 International Conference on Intelligent Data Communication Technologies and Internet of Things Proceedings, 2023
    A rise in the number and devastating capability of hardware-based assaults has brought attention to the necessity of protecting the hardware root of trust alongside improvements in power, cost, performance, and reliability. The whole design of an integrated circuit can be concealed from a suspect foundry or end- user via a key-based circuit obfuscation or logic-locking approach. The method is based on introducing "key" input bits into the circuit to introduce ambiguity within the original circuit, rendering the circuit unreadable without the proper secret key. The present level of knowledge in this developing area is reviewed in this study, which also includes a threat model classification such as hardware Trojans, re verse engineering (RE) and side channel analysis. Moreover, the traditional and strong logic locking techniques and its efficiency in terms of area, power, delay is reviewed in hardware-based attacks.
  • REVIEW ON RESISTIVE RANDOM ACCESS MEMORY BASED PHYSICAL UNCLONABLE FUNCTION CIRCUITS FOR HIGH SECURITY*
    Procedia Environmental Science Engineering and Management, 2023
  • Biometric-Based Key Generation Using AES Algorithm for Real-Time Security Applications
    S. Sridevi Sathya Priya, N. M. Sivamangai, R. Naveenkumar, A. Napolean, G. Saranya
    Homomorphic Encryption for Financial Cryptography Recent Inventions and Challenges, 2023
  • Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications
    R. Naveenkumar, N. M. Sivamangai, A. Napolean, S. Sridevi Sathya Priya
    Journal of Electronic Testing Theory and Applications JETTA, 2022
  • Electroforming Atmospheric Temperature and Annealing Effects on Pt/HfO2/TiO2/HfO2/Pt Resistive Random Access Memory Cell
    A. Napolean, N. M. Sivamangai, R. NaveenKumar, N. Nithya
    Silicon, 2022
  • Review on role of nanoscale HfO2 switching material in resistive random access memory device
    N. A, Sivamangai Nm, R. S., N. R, N. N, K. S, A. N
    Emergent Materials, 2022
  • Hardware Obfuscation for IP Protection of DSP Applications
    Naveenkumar R, N.M. Sivamangai, Napolean A, G. Akashraj Nissi
    Journal of Electronic Testing Theory and Applications JETTA, 2022
  • Effects of Ambient and Annealing Temperature in HfO2Based RRAM Device Modeling and Circuit-Level Implementation
    A. Napolean, N. M. Sivamangai, S. Rajesh, R. Naveenkumar, N. Sharon, N. Nithya, S. Kamalnath
    Ecs Journal of Solid State Science and Technology, 2022
  • Mathematical Modeling of Annealed Trilayer Oxide-Based Memristor Device
    K. Paramasivam, N. Nithya, A. Napolean
    VLSI Sata 2022 3rd IEEE International Conference on VLSI Systems Architecture Technology and Applications, 2022
  • Preventive Measure of SAT Attack by Integrating Anti-SAT on Locked Circuit for Improving Hardware Security
    R Naveenkumar, N.M Sivamangai, A Napolean, A. Puviarasu, G Saranya
    7th International Conference on Communication and Electronics Systems Icces 2022 Proceedings, 2022
  • Effect of Indium concentration in Multiple Quantum Well based InGaN/GaN Light Emitting Diode using TCAD
    G Saranya, N M Siva Mangai, A Napolean, R Naveenkumar, B Priya
    Icdcs 2022 2022 6th International Conference on Devices Circuits and Systems, 2022
  • Review on Arbiter Physical Unclonable Function and its Implementation in FPGA for IoT Security Applications
    Sk. Shariffuddin, N.M Sivamangai, A Napolean, R Naveenkumar, S Kamalnath, G Saranya
    Icdcs 2022 2022 6th International Conference on Devices Circuits and Systems, 2022
  • Review on Logic Locking Attacks in Hardware Security
    J Jemimah Rinsy, N.M. Sivamangai, R Naveenkumar, A Napolean, A. Puviarasu, V. Janani
    Icdcs 2022 2022 6th International Conference on Devices Circuits and Systems, 2022
  • A survey on recent detection methods of the hardware trojans
    R Naveenkumar, N.M Sivamangai, A Napolean, V Janani
    2021 3rd International Conference on Signal Processing and Communication Icpsc 2021, 2021
  • A Novel Hybrid CMOS-Memristor Based 2-Bit Magnitude Comparator using Memristor Ratioed Logic Universal Gate for Low Power Applications
    K. Paramasivam, N. Nithya, A. Nepolean
    2021 International Conference on Advancements in Electrical Electronics Communication Computing and Automation Icaeca 2021, 2021
  • Temperature effects on an HfO2-TiO2-HfO2 stack layer resistive random access memory cell for low power applications
    A. Napolean, N.M. Sivamangai, R. NaveenKumar
    Icdcs 2020 2020 5th International Conference on Devices Circuits and Systems, 2020
  • Overview of Current Compliance Effect on Reliability of Nano Scaled Metal Oxide Resistive Random Access Memory Device
    A. Napolean, N. M. Sivamangai, Joel Samuel, Vimukth John
    Proceedings of the 4th International Conference on Devices Circuits and Systems Icdcs 2018, 2019
  • An optimal non invasive blood glucose measurement using Smartphone by near infrared spectroscopy
    International Journal of Applied Engineering Research, 2015
  • A novel converter topology for stand-alone hybrid PV/Wind/battery power system using Matlab/Simulink
    S. Ramya, A. Napolean, T. Manoharan
    Proceedings of 2013 International Conference on Power Energy and Control Icpec 2013, 2013

RECENT SCHOLAR PUBLICATIONS

  • Implementation of RSA Algorithm for Cryptography in Hardware Security
    R Naveenkumar, NM Sivamangai, SS Sathyapriya, A Napolean
    National Academy Science Letters, 1-6 , 2026
    2026
  • Securing DSP IPs: A Comprehensive Study on Logic and Structural Obfuscation Techniques
    R Naveenkumar, NM Sivamangai, SS Sathayapriya, A Napolean
    National Academy Science Letters, 1-6 , 2026
    2026
  • Quantum Computing Transforming Machine Learning: An Overview
    NM Sivamangai, R Naveenkumar, NM Kishore, CM Lingesh, A Napolean, ...
    Quantum Computing, 19-54 , 2026
    2026
  • Design of energy-efficient hybrid STT-MTJ/CMOS-based LIM logic gates for IoT applications
    N Aswathy, NM Sivamangai, A Napolean, T Jarin
    Measurement: Sensors 32, 101063 , 2024
    2024
    Citations: 4
  • Measurement: sensors
    N Aswathy, NM Sivamangai, A Napolean, T Jarin
    Measurement 32, 101063 , 2024
    2024
    Citations: 1
  • Review on Hardware Trojan Detection Techniques: R. Naveenkumar et al.
    R Naveenkumar, NM Sivamangai, A Napolean, S Sridevi Sathayapriya
    National Academy Science Letters 46 (6), 521-524 , 2023
    2023
    Citations: 5
  • Biometric-based key generation using aes algorithm for real-time security applications
    S Sridevi Sathya Priya, NM Sivamangai, R Naveenkumar, A Napolean, ...
    Homomorphic Encryption for Financial Cryptography: Recent Inventions and … , 2023
    2023
    Citations: 3
  • Enhancing Encryption Security Against Cypher Attacks
    R Naveenkumar, NM Sivamangai, A Napolean, S Sridevi Sathyapriya
    Homomorphic Encryption for Financial Cryptography: Recent Inventions and … , 2023
    2023
    Citations: 1
  • Design of INV/BUFF logic locking for enhancing the hardware security
    R Naveenkumar, NM Sivamangai, A Napolean, SSS Priya, SV Ashika
    Journal of Electronic Testing 39 (2), 141-153 , 2023
    2023
    Citations: 3
  • Importance of logic locking attacks in hardware security
    SV Ashika, NM Sivamangai, R Naveenkumar, A Napolean
    2023 International Conference on Intelligent Data Communication Technologies … , 2023
    2023
    Citations: 7
  • Review on resistive random access memory based physical unclonable function circuits for high security
    A Napolean, NM Sivamangai, N Sharon, R Naveen Kuma
    Procedia Environ. Sci. Eng. Manag 10 (1), 41-52 , 2023
    2023
    Citations: 1
  • Mathematical Modeling of Annealed Trilayer Oxide-Based Memristor Device
    K Paramasivam, N Nithya, A Napolean
    2022 IEEE 3rd International Conference on VLSI Systems, Architecture … , 2022
    2022
    Citations: 1
  • Design and evaluation of XOR arbiter physical unclonable function and its implementation on FPGA in hardware security applications
    R Naveenkumar, NM Sivamangai, A Napolean, SSS Priya
    Journal of Electronic Testing 38 (6), 653-666 , 2022
    2022
    Citations: 21
  • Preventive measure of sat attack by integrating anti-sat on locked circuit for improving hardware security
    R Naveenkumar, NM Sivamangai, A Napolean, A Puviarasu, G Saranya
    2022 7th International Conference on Communication and Electronics Systems … , 2022
    2022
    Citations: 14
  • Review on arbiter physical unclonable function and its implementation in FPGA for IoT security applications
    S Shariffuddin, NM Sivamangai, A Napolean, R Naveenkumar, ...
    2022 6th International Conference on Devices, Circuits and Systems (ICDCS … , 2022
    2022
    Citations: 11
  • Review on logic locking attacks in hardware security
    JJ Rinsy, NM Sivamangai, R Naveenkumar, A Napolean, A Puviarasu, ...
    2022 6th International Conference on Devices, Circuits and Systems (ICDCS … , 2022
    2022
    Citations: 8
  • Effect of Indium concentration in Multiple Quantum Well based InGaN/GaN Light Emitting Diode using TCAD
    G Saranya, NMS Mangai, A Napolean, R Naveenkumar, B Priya
    2022 6th International Conference on Devices, Circuits and Systems (ICDCS … , 2022
    2022
  • Electroforming Atmospheric Temperature and Annealing Effects on Pt/HfO 2 /TiO 2 /HfO 2 /Pt Resistive Random Access Memory Cell
    A Napolean, NM Sivamangai, R Naveenkumar, N Nithya
    Silicon 14 (6), 2863-2869 , 2022
    2022
    Citations: 14
  • Hardware obfuscation for IP protection of DSP applications
    NM Sivamangai, GA Nissi
    Journal of Electronic Testing 38 (1), 9-20 , 2022
    2022
    Citations: 16
  • Effects of Ambient and Annealing Temperature in HfO 2 Based RRAM Device Modeling and Circuit-Level Implementation
    A Napolean, NM Sivamangai, S Rajesh, R Naveenkumar, N Sharon, ...
    ECS Journal of Solid State Science and Technology 11 (2), 023012 , 2022
    2022
    Citations: 3

MOST CITED SCHOLAR PUBLICATIONS

  • A survey on recent detection methods of the hardware trojans
    R Naveenkumar, NM Sivamangai, A Napolean, V Janani
    2021 3rd International conference on signal processing and communication … , 2021
    2021
    Citations: 27
  • Design and evaluation of XOR arbiter physical unclonable function and its implementation on FPGA in hardware security applications
    R Naveenkumar, NM Sivamangai, A Napolean, SSS Priya
    Journal of Electronic Testing 38 (6), 653-666 , 2022
    2022
    Citations: 21
  • Fabrication Of Thin Film Transistor Using High K Dielectric Materials
    CR Napolean
    International Journal Of Engineering And Computer Science ISSN:2319-7242 3 … , 2014
    2014
    Citations: 19
  • Hardware obfuscation for IP protection of DSP applications
    NM Sivamangai, GA Nissi
    Journal of Electronic Testing 38 (1), 9-20 , 2022
    2022
    Citations: 16
  • Preventive measure of sat attack by integrating anti-sat on locked circuit for improving hardware security
    R Naveenkumar, NM Sivamangai, A Napolean, A Puviarasu, G Saranya
    2022 7th International Conference on Communication and Electronics Systems … , 2022
    2022
    Citations: 14
  • Electroforming Atmospheric Temperature and Annealing Effects on Pt/HfO 2 /TiO 2 /HfO 2 /Pt Resistive Random Access Memory Cell
    A Napolean, NM Sivamangai, R Naveenkumar, N Nithya
    Silicon 14 (6), 2863-2869 , 2022
    2022
    Citations: 14
  • A novel converter topology for stand-alone hybrid PV/Wind/battery power system using Matlab/Simulink
    S Ramya, A Napolean, T Manoharan
    2013 International Conference on Power, Energy and Control (ICPEC), 17-22 , 2013
    2013
    Citations: 12
  • Review on arbiter physical unclonable function and its implementation in FPGA for IoT security applications
    S Shariffuddin, NM Sivamangai, A Napolean, R Naveenkumar, ...
    2022 6th International Conference on Devices, Circuits and Systems (ICDCS … , 2022
    2022
    Citations: 11
  • Review on logic locking attacks in hardware security
    JJ Rinsy, NM Sivamangai, R Naveenkumar, A Napolean, A Puviarasu, ...
    2022 6th International Conference on Devices, Circuits and Systems (ICDCS … , 2022
    2022
    Citations: 8
  • Importance of logic locking attacks in hardware security
    SV Ashika, NM Sivamangai, R Naveenkumar, A Napolean
    2023 International Conference on Intelligent Data Communication Technologies … , 2023
    2023
    Citations: 7
  • Review on Hardware Trojan Detection Techniques: R. Naveenkumar et al.
    R Naveenkumar, NM Sivamangai, A Napolean, S Sridevi Sathayapriya
    National Academy Science Letters 46 (6), 521-524 , 2023
    2023
    Citations: 5
  • Overview of current compliance effect on reliability of nano scaled metal oxide resistive random access memory device
    A Napolean, NM Sivamangai, J Samuel, V John
    2018 4th International Conference on Devices, Circuits and Systems (ICDCS … , 2018
    2018
    Citations: 5
  • Design of energy-efficient hybrid STT-MTJ/CMOS-based LIM logic gates for IoT applications
    N Aswathy, NM Sivamangai, A Napolean, T Jarin
    Measurement: Sensors 32, 101063 , 2024
    2024
    Citations: 4
  • Biometric-based key generation using aes algorithm for real-time security applications
    S Sridevi Sathya Priya, NM Sivamangai, R Naveenkumar, A Napolean, ...
    Homomorphic Encryption for Financial Cryptography: Recent Inventions and … , 2023
    2023
    Citations: 3
  • Design of INV/BUFF logic locking for enhancing the hardware security
    R Naveenkumar, NM Sivamangai, A Napolean, SSS Priya, SV Ashika
    Journal of Electronic Testing 39 (2), 141-153 , 2023
    2023
    Citations: 3
  • Effects of Ambient and Annealing Temperature in HfO 2 Based RRAM Device Modeling and Circuit-Level Implementation
    A Napolean, NM Sivamangai, S Rajesh, R Naveenkumar, N Sharon, ...
    ECS Journal of Solid State Science and Technology 11 (2), 023012 , 2022
    2022
    Citations: 3
  • Measurement: sensors
    N Aswathy, NM Sivamangai, A Napolean, T Jarin
    Measurement 32, 101063 , 2024
    2024
    Citations: 1
  • Enhancing Encryption Security Against Cypher Attacks
    R Naveenkumar, NM Sivamangai, A Napolean, S Sridevi Sathyapriya
    Homomorphic Encryption for Financial Cryptography: Recent Inventions and … , 2023
    2023
    Citations: 1
  • Review on resistive random access memory based physical unclonable function circuits for high security
    A Napolean, NM Sivamangai, N Sharon, R Naveen Kuma
    Procedia Environ. Sci. Eng. Manag 10 (1), 41-52 , 2023
    2023
    Citations: 1
  • Mathematical Modeling of Annealed Trilayer Oxide-Based Memristor Device
    K Paramasivam, N Nithya, A Napolean
    2022 IEEE 3rd International Conference on VLSI Systems, Architecture … , 2022
    2022
    Citations: 1