Napolean A
@aiet.org.in
Sr Assistant Professor in the Dept of ECE
Alvas Institute of Engineering and Technology
RESEARCH, TEACHING, or OTHER INTERESTS
Electrical and Electronic Engineering, Automotive Engineering, Electronic, Optical and Magnetic Materials, Computer Networks and Communications
Scopus Publications
Scholar Citations
Scholar h-index
Scholar i10-index
Scopus Publications
R. Naveenkumar, N. M. Sivamangai, A. Napolean, and S. Sridevi Sathayapriya
Springer Science and Business Media LLC
R. Naveenkumar, N. M. Sivamangai, A. Napolean, S. Sridevi Sathya Priya, and S. V. Ashika
Springer Science and Business Media LLC
Ashika S V, N. M. Sivamangai, R Naveenkumar, and Napolean A
IEEE
A rise in the number and devastating capability of hardware-based assaults has brought attention to the necessity of protecting the hardware root of trust alongside improvements in power, cost, performance, and reliability. The whole design of an integrated circuit can be concealed from a suspect foundry or end- user via a key-based circuit obfuscation or logic-locking approach. The method is based on introducing "key" input bits into the circuit to introduce ambiguity within the original circuit, rendering the circuit unreadable without the proper secret key. The present level of knowledge in this developing area is reviewed in this study, which also includes a threat model classification such as hardware Trojans, re verse engineering (RE) and side channel analysis. Moreover, the traditional and strong logic locking techniques and its efficiency in terms of area, power, delay is reviewed in hardware-based attacks.
R. Naveenkumar, N. M. Sivamangai, A. Napolean, and S. Sridevi Sathya Priya
Springer Science and Business Media LLC
N. A, Sivamangai Nm, R. S., N. R, N. N, K. S and A. N
Springer Science and Business Media LLC
A. Napolean, N. M. Sivamangai, R. NaveenKumar, and N. Nithya
Springer Science and Business Media LLC
Naveenkumar R, N.M. Sivamangai, Napolean A, and G. Akashraj Nissi
Springer Science and Business Media LLC
A. Napolean, N. M. Sivamangai, S. Rajesh, R. Naveenkumar, N. Sharon, N. Nithya, and S. Kamalnath
The Electrochemical Society
This article focuses on the relevance of the effect of ambient temperature and annealing in the context of compact modeling of metal oxide resistive random access memory (RRAM) devices. The ambient temperature affects the conduction characteristic of resistive switching memories, so it becomes an essential factor to include when adjusting the experimental data. Reported the fabricated results and memory switching parameters with the defined set (Vset) and reset (Vreset) transition voltages for the fabricated annealed HfO2-based RRAM. Additionally, to illustrate the importance of this characteristic in the form of the I-V curve, the Stanford model (SFM) for RRAM devices is enhanced by incorporating the annealing temperature as an additional parameter in the script of the Verilog-A model. Stanford and modified Stanford model (MSFM) are analyzed at the device level using cadence circuit simulator and implemented in the nonvolatile memory circuit (3 *3 memory arrays). Results confirmed that the experimental switching voltages, Vset, Vreset are 1.7 V, −0.8 V. These values are well suited along the simulated MSFM switching voltages of, Vset, Vreset (1.8 V, −0.7 V). The mean error percentage of the MSF is 18.42%.
K. Paramasivam, N. Nithya, and A. Napolean
IEEE
This paper focuses on the mathematical modeling of tri-layer HfO2/TiO2/HfO2-based RRAM devices. Memristor, which is also known as RRAM device is the new generation non-volatile memory device. It is a passive element that establishes the relation between charge and flux. The literature survey portrays that the fractional order memristor models are not compatible with SPICE coding and first order RRAM models have limitations in elucidating the RRAM device’s oscillation behavior. A mathematical approach using is adopted to validate the empirically extracted results. The main advantages are window functions with fewer fitting parameters are used for the Biolek window function combined with the VTEAM model to overcome the boundary problems.
R Naveenkumar, N.M Sivamangai, A Napolean, A. Puviarasu, and G Saranya
IEEE
The use of logic locking to combat piracy is a viable option and counterfeiting of outsourced IC design by unreliable foundries. Even when a secure key is supplied a locked IC enable the proper functioning. However, a new assault known as the SAT attack threatens its security, as it can decrypt the appropriate key for the most logic locking methods in a short span of time, even if there are a lot of keys. SAT attacks degrade the security by breaking the formulae sequentially, rejecting wrong keys one by one until the circuit is unlocked. These issues are solved by The Anti-SAT block (ASB) is a technique for improving the protection of traditional logic locking approaches it in opposition to SAT attack. The objective of this paper is to overcome issues of piracy, counterfeiting, and SAT attacks. Develop the security in opposition to SAT attacks through the Anti-Sat circuit block with obfuscation technique. Proposed Anti -Sat based structural obfuscation for C17 benchmark with iterations. Experimental results confirm that the suggested XOR/XNOR logic locking anti-sat with structural obfuscation concept enhances the security with an iteration perspective. Moreover, the amount of SAT attack repetitions needed to expose a proper key in a circuit including an Anti-Sat Block is proportional to the key-size, computationally, the SAT attack is unachievable.
G Saranya, N M Siva Mangai, A Napolean, R Naveenkumar, and B Priya
IEEE
In the proposed work, the molar concentration of indium is varied for InGan/GaN Light Emitting Diode (LED). Technological computer aided design (TCAD) physical simulator is used to simulate the various electrical and optical parameters of the device. From the simulation, it is understood that the higher concentration affects the device performance. The mole fraction of indium is preferred to tak8e 0.1 to get higher luminous power, radiative and recombination rate. InGan/GaN LED with less indium content is advisable for the fields like indoor and outdoor lightening applications.
J Jemimah Rinsy, N.M. Sivamangai, R Naveenkumar, A Napolean, A. Puviarasu, and V. Janani
IEEE
Increasing threats involving hardware Trojans, intellectual property, piracy, reverse engineering and industrialization of semiconductor technology have forced semiconductor companies to reevaluate their production chain trust. In response to these dangers, logic locking is becoming a well-known and effective countermeasure to hardware security. All present logic locking techniques can be broken in hours by a SAT-based attack. Anti-SAT blocks, along with a locked circuit, are introduced as improvements to current logic locking technologies. Sat iterations are proportional to key length and therefore require a certain number to expose the right key, the circuit is computationally infeasible. The paper focus on various logic locking attacks in hardware security.
Sk. Shariffuddin, N.M Sivamangai, A Napolean, R Naveenkumar, S Kamalnath, and G Saranya
IEEE
Security is one of the most difficult aspects of advancing the Internet of Things (IoT) in our daily lives and future industrial systems. IoT systems have a variety a slew of issues, including a scarcity of resources, reduced power usage, and the necessity to secure devices from cyber-attacks. Unfortunately, the approaches are limited by power consumption and a lack of computer capabilities; also, the typical usage of non-volatile memory to store secret keys is open to several assaults such as reverse engineering and side channeling. PUFs (Physical Unclonable Functions) are a type of method that is used to increase the security of physical devices and solve problems connected with existing cryptographic algorithms. PUFs are one-way lightweight functions that extort a distinct personality for each terminal based on unpredictable and impossible to reproduce physical variables imposed during production. Memory-based PUF’s (e.g., SRAM and SR-latch PUF’s), delay-based PUF’s (e.g., Arbiter PUF (APUF), digital PUF’s, operating frequency-based PUF’s (ring oscillator PUF (ROPUF)), and other PUF’s have been achieved in ASIC and, FPGA in particular. In this article, we examine a wide range of PUFs found in the literature. Many observations are based on the comparison of the surveyed schemes. The review concentrates on different types of arbiter PUF architectures and the quality of the designed arbiter PUFs in terms of three parameters: reliability, uniqueness and uniformity. This study examines the latest Arbiter PUF innovations and the necessary security requirements and promising security solutions for IoT applications.
R Naveenkumar, N.M Sivamangai, A Napolean, and V Janani
IEEE
Modern integrated circuit design contains various constraints from the frontend to the backend. In microelectronic systems hardware security is a major threat. Hardware Trojan (HT) plays a vital role in hardware security issues. The HT leads to a malicious modification of the integrated circuit (IC). The HT detection aims to assure the trustworthiness of the circuits and improve the reliability of the system. In this article, we presented a review of the various hardware detection techniques like pre-deployment, post-deployment, formal verification, counterfeiting prevention and IC production, physically-unclonable function HT detection techniques. Moreover, HT parameters are analyzed for specific benchmarks.
K. Paramasivam, N. Nithya, and A. Nepolean
IEEE
In recent years, memristor-based digital circuit design has become one of the prime focuses for low power, area-efficient VLSI design. A comparator is a combinational circuit used in complex ALU for the comparison of n-bit numbers. The unique hybrid 2bit CMOS-based comparator with Memristor Ratioed Logic Universal Gates has been implemented in this study (MRLUG). The proposed 2-bit magnitude comparator is verified by theoretical analysis and SPICE simulations. The area on-chip and power analysis are performed and the results are compared with conventional CMOS logic and threshold logic-based magnitude comparator. The feasibility of the proposed design is analyzed using LTSPICE and simulation results show an average power consumption of $39.92\\mu \\mathrm{W}$ and 32.14% improvement in the area compared to resistive threshold logic (RTL).
A. Napolean, N.M. Sivamangai, and R. NaveenKumar
IEEE
In this paper we analyzed the forming voltage (Vf) and resistive switching characteristics of the fabricated nano structured trilayer resistive switching device (Pt/HfO2/TiO2/HfO2/Pt). Standard fabrication process is opted with a post metal annealing (PMA) process to diminish the forming voltages of stack layer resistive random access memory (RRAM) cells. Result reveals after the post metal annealing, the Vf is reduced to 3.6 V from 4.4 V at room temperature (25°C). In addition at high background temperature (80°C) the Vf value is diminished significantly (3.2 V) compared to lower temperatures, 50° C and 25° C. We optimized, the forming environment temperature (80° C), compliance current (30 µA) for the further reduction of Vf value.
A. Napolean, N. M. Sivamangai, Joel Samuel, and Vimukth John
IEEE
This review contribute the consequence of compliance current (CC) on a widely used metal oxide Resistive Random Access Memory (RRAM) device distinctive characteristics of resistive switching and reliability. Article starts with the current trends of RRAM technology, then short knowledge about different nonvolatile memory technology forces to limit, RRAM device structure, switching principles, material selection and reliability controversy. Next a detailed short account of CC value with other RRAM device measure. This review ends with the decisive of electing an optimized CC value for a superior switching and reliability.
S. Ramya, A. Napolean, and T. Manoharan
IEEE
The objective of this paper is to propose a multi-input power converter for the hybrid system that interfaces two unidirectional ports for input power sources, a bidirectional port for a storage element, and a port for output load in a unified structure. The two input ports for simultaneously converting two different input power sources with low voltages to a stable output power with a high voltage. According to various situations, the operational states of the proposed converter can be divided into three states based on battery utilization. In order to ensure that the system operates with high efficiency, this paper proposes a power management control scheme, which controls the bidirectional converter operating under boost mode according to the operation condition of the PV/Wind, so that the battery can be charged or discharged. The integration of the hybrid renewable power system is implemented and simulated using MATLAB/SIMULINK.