Keerthy Rai V

Scopus Publications

An Efficient Deep Learning based Waste Management System for Sustainable Environment
Saghana K, Saranya P, Mahesh Reddy A, Keerthy Rai V, Ramasubramanian B, et al.
3rd International Conference on Intelligent Data Communication Technologies and Internet of Things Idciot 2025, 2025
Efficient Management of solid and liquid waste is crucial for maintaining environmental sustainability and public health. This work presents a novel approach for the detection and segregation of solid and liquid waste using deep learning techniques. By leveraging Convolutional Neural Networks (CNNs), a system is designed which is capable of automatically classifying waste into solid or liquid categories based on real-time image data from waste disposal units. The system also integrates Internet of Things (IoT) devices to transmit the classified waste data to a remote central collection centre for optimized disposal processes. The model was trained on a diverse dataset of waste images and achieved high accuracy in distinguishing between solid and liquid waste. Once classified, the waste information is communicated via a secure wireless network to the central collection centre, which can coordinate timely collection and disposal efforts. This approach not only automates the waste management process but also reduces manual errors and delays in waste segregation and disposal. This work also discusses the potential for scalability and implementation in smart city infrastructures. Compared to the state of art method existing in the literature, this proposed method achieves an accuracy of 98.31 %, Precision of 97.93%, recall of 98.17% with a F1- score of 0.98. This system demonstrates the effectiveness of deep learning in waste classification and proposes a scalable solution for enhancing waste management practices, ultimately contributing to a more sustainable environment.
Neuron Network with a Synapse of CMOS transistor and Anti-Parallel Memristors for Low power Implementations
V. Keerthy Rai, R. Sakthivel
Journal of Circuits Systems and Computers, 2022
The bio-mimetic structure of a neuron is taken into account for utilizing the electrophysiological data. These neuron circuits are entertained for the use in digital computers. At the end of Moore’s law, conventional technology is striking different difficulties, such as power consumption, area utilization, and energy efficiency. To conquer these hurdles, a nanoscale, the nonvolatile memristor used in the proposed neuron modified from the refined AH neuron. Synapses are also built using anti-parallel memristors. These neurons and synapse are joined together such that the performance metrics are analyzed the energy consumption is reduced by 89.656%. Besides, power consumption is limited by 37.568% and the spike frequency is measured as 10.263[Formula: see text]kHz when compared with the traditional CMOS synapse connected with the proposed neuron. Moreover, the measured energy per spike is 3.37[Formula: see text]fJ. The implementation of the neuron network is done by 45[Formula: see text]nm technology.
Designs protracted to combinational and sequential circuits by using hybrid MOS transistor with memristor
V Keerthy Rai, Sakthivel R
International Journal of Advanced Technology and Engineering Exploration, 2021
A resistive device with a memory characteristic feature entitled memristor is explored to overcome the limitations of the Complementary Metal Oxide Semiconductor (CMOS) technology scaling. The memristor is utilized in place of the Metal Oxide Semiconductor (MOS) transistor due to its non-volatile character and nano-scale element. Thus, researchers worked on a combination of memristor and MOS transistor affords with reduced area exploitation, reduced power dissipation, reliability, and large density. At this juncture, the design of an XOR gate with P-channel Metal Oxide Semiconductor (PMOS) transistors and memristors is accomplished. This design is implemented in 90nm CMOS technology in Cadence Virtuoso and simulations are brought about Spectre. The power dissipation and delay are reduced when compared with conventional CMOS XOR gate. Finally, it is used in full adder design. The average power dissipation is reduced by 69.32%. Further, some of the combinational and sequential circuits like 8×1 Multiplexer (MUX), 1×8 De-multiplexer (DEMUX), and 4-bit Universal Shift Register (USR) are developed. The power of 8×1 MUX is reduced by 43.7 % and the power of 1×8 DEMUX is decreased by 30 % when compared with the conventional designs. The sequential circuit of 4-bit USR is also designed and power is limited by 10.76%. The delay is improved by 79.39% for the proposed 4-bit USR. Improvement of power and delay is observed when compared with the traditional designs.
Design of artificial neuron network with synapse utilizing hybrid CMOS transistors with memristor for low power applications
V. Keerthy Rai, R. Sakthivel
Journal of Circuits Systems and Computers, 2020
Neural networks are mimetic with biological neuron which are employed on digital computers. These networks are designed with CMOS technology using 0.45[Formula: see text][Formula: see text]m in cadence virtuoso. The scaling of CMOS limits parameters like power consumption, area and parallelism. To overcome the limitations, a nanoscale, nonvolatile Memristor device is used to design the synapses. The proposed network is designed for neuron synapse networks implemented with a memristor device. This network is compared with neuron linked with CMOS synapse. The proposed network has low power consumption, high spike frequency, and low delay value. The spike frequency of Memristor synapse increases by 65.51% when compared with the existing CMOS synapse and power consumption is reduced to 52.79%. The delay is reduced to 0.294[Formula: see text][Formula: see text]s. The simulation results are carried using Specter.

RECENT SCHOLAR PUBLICATIONS

Designs protracted to combinational and sequential circuits by using hybrid MOS transistor with memristor
VK Rai, R Sakthivel
International Journal of Advanced Technology and Engineering Exploration 8 … , 2021
2021.0
Citations: 3
Design of artificial neuron network with synapse utilizing hybrid CMOS transistors with memristor for low power applications
VK Rai, R Sakthivel
Journal of Circuits, Systems and Computers 29 (12), 2050187 , 2020
2020.0
Citations: 15
Implementation of D-flipflop using Hybrid Memristor with CMOS Transistor
VK RAI
HELIX 10 (2), 143-146 , 2020
2020.0
Citations: 1
Survey based on Comparison of different CMOS logic styles with Hybrid CMOS Memristor Logic Style with issues and parameters
SR Keerthy Rai V
International Journal of Pure and Applied Mathematics 118 (No. 18), 4373-4392 , 2018
2018.0
Static Power Reduction using Reconfigurable Multi-Mode VTCMOS Switches
B MUNILAKSHMI, R KALYAN, VK RAI
2014.0
Implementation of Adder by using FPGA with Low Power Consumption and Area
N SINDHURA, UB LAKSHMI, VK RAI, M PADMAJA
A Novel Approach to Condense the Leakage Power in Deep Submicron Circuits by Sleep Methods
R Padmasena, R Kalyan, VK Rai

MOST CITED SCHOLAR PUBLICATIONS

Design of artificial neuron network with synapse utilizing hybrid CMOS transistors with memristor for low power applications
VK Rai, R Sakthivel
Journal of Circuits, Systems and Computers 29 (12), 2050187 , 2020
2020.0
Citations: 15
Designs protracted to combinational and sequential circuits by using hybrid MOS transistor with memristor
VK Rai, R Sakthivel
International Journal of Advanced Technology and Engineering Exploration 8 … , 2021
2021.0
Citations: 3
Implementation of D-flipflop using Hybrid Memristor with CMOS Transistor
VK RAI
HELIX 10 (2), 143-146 , 2020
2020.0
Citations: 1
Survey based on Comparison of different CMOS logic styles with Hybrid CMOS Memristor Logic Style with issues and parameters
SR Keerthy Rai V
International Journal of Pure and Applied Mathematics 118 (No. 18), 4373-4392 , 2018
2018.0
Static Power Reduction using Reconfigurable Multi-Mode VTCMOS Switches
B MUNILAKSHMI, R KALYAN, VK RAI
2014.0
Implementation of Adder by using FPGA with Low Power Consumption and Area
N SINDHURA, UB LAKSHMI, VK RAI, M PADMAJA
A Novel Approach to Condense the Leakage Power in Deep Submicron Circuits by Sleep Methods
R Padmasena, R Kalyan, VK Rai