RATHINAM A
@pec.paavai.edu.in
PROFESSOR AND ELECTRICAL AND ELECTRONICS ENGINEERING/
PAAVAI ENGINEERING COLLEGE
EDUCATION
Ph.D Electrical (Multilevel Inverter) Anna university, Chennai.
M.E Power Electronics and Drives K.S.Rangasamy College of Technology, Tiruchengode.
B.E EEE Government College of Engineering, Salem.
RESEARCH INTERESTS
Power Electronics and dsrives
Scopus Publications
Scholar Citations
Scholar h-index
Scholar i10-index
Scopus Publications
M. Karthick, A. Rathinam, and S. Vadivel
Springer Science and Business Media LLC
M. Karthick, A. Rathinam, and S. Vadivel
Springer Science and Business Media LLC
G. Balaji, A. Rathinam, and S. Vadivel
Springer Science and Business Media LLC
A. Rathinam, G. Balaji, and S. Vadivel
Springer Science and Business Media LLC
Ramani Kannan, Rathinam Angamuthu, and K. Y. Ahmed
IEEE
The multilevel inverter technology introduced for medium and high voltage, high power applications. This paper is proposed to control the diode clamp multilevel inverter by using a synchronous sequential circuit for photo energy conversion. The performance of the multilevel inverter has been improved in-terms of minimum output harmonics distortion, simpler structure, effortless fault identification, cost-effectiveness and low power consumption. This new control strategy has maintained the balanced voltages on the dc link capacitors. PV based five-level diode clamped multilevel inverter has been validated with single induction motor drive through MATLAB/Simulink simulation and tested experimentally through the prototype model.
A. Rathinam, T. Karthikeyan, and K. Ramani
MAFTREE
This paper focused with extends the knowledge in studies and analysis of a new family of diode clamp multilevel inverter for electric vehicle application. The modified new diode clamp multilevel inverter concepts is related to reducing the components utilization, which has (n-1) switching devices, (n-3) clamping diodes, (n-1)/2 DC-link sources for achieving the same voltage level of traditional topologies. The proposed system is enhanced the voltage rating and reduce the total harmonics distortion in inverter output voltage. The switching scheme of Alternatively on Opposition Disposition pulse width modulation strategies is implemented to control multilevel inverter. The proposed system reduces the components utilization which has utilizes 45% of components for achieving the same level of voltage. The modified new diode clamp multilevel inverter is coupled with induction motor and its performance is validated with three phase induction motor for variable frequency drive. The inverter topologies performance has been investigated by prototype model.
Rathinam Angamuthu, Karthikeyan Thangavelu, and Ramani Kannan
The Institute of Electronics Engineers of Korea
This paper describes the design and implementation of a new diode clamped multilevel inverter for variable frequency drive. The diode clamp multilevel inverter has been widely used for low power, high voltage applications due to its superior performance. However, it has some limitations such as increased number of switching devices and complex PWM control. In this paper, a new topology is proposed. New topology requires only (N-1) switching devices and (N-3) clamping diodes compared to existing topology. A modified APO-PWM control method is used to generate gate pulses for inverter. The proposed inverter topology is coupled with single phase induction motor and its performance is tested by MATLAB simulation. Finally, a prototype model has built and its performance is tested with single phase variable frequency drive.
R. Kannan, A. Rathinam, Z.B.H. Baharudi, and T. Karthikeyan
Institution of Engineering and Technology
A. Rathinam, K. Ramani, and T. Karthikeyan
IEEE
This paper focus on switching pattern selection scheme based cascaded multilevel inverter fed induction motor drive. It offer several advantages compared to the conventional 3-phase bridge inverter in terms of lower dv/dt stresses, lower electromagnetic compatibility, smaller rating and better output features. The proposed method has been designed an eleven-level cascaded multilevel inverter by using sinusoidal pulse width modulation technique. The selected pattern has been exposed to give superior performance in load voltage, total harmonics distortion and capacitor voltage fluctuation. The performance of proposed strategies is confirmed through simulation and hardware investigations.