Ph.D. in Electronics and Communication Engineering from National Institute of Technology Silchar (2022)
M.Tech in Electronics Design and Technology from Tezpur University (2016)
B.E in Electronics and Tele-Communication Engineering from Gauhati University (2013)
12th from State Board (2009)
10th from State Board (2007)
RESEARCH INTERESTS
Analog VLSI Circuit Design, Biomedical Circuits and Optimization Methods
Preface Exploring the Intricacies of Digital and Analog VLSI, 2025
Optimizing CMOS inverter characteristics with evolutionary algorithm strategies Paramita Sarkar, Harish Sharma Akkera, Sabina Rahaman, Neeraj Kumar Niranjan, Swagata Devi Exploring the Intricacies of Digital and Analog VLSI, 2025 This work uses the Dragonfly Algorithm (DA) and Drosophila Food Search Optimization (DFO) to enhance the switching characteristics of CMOS technology. Inspired by the food-search behavior of Drosophila Melanogaster and Dragonflies, both algorithms optimize single- and multi-objective problems and are compared with Whale Optimization Algorithm (WOA) and Particle Swarm Optimization (PSO). The study focuses on identifying optimal design variables for a CMOS inverter with symmetric switching. DA and DFO were further tested on a differential amplifier with a current mirror load, demonstrating their effectiveness in more complex circuits. The solutions were verified using SYNOPSYS HSPICE with UMC 180nm process technology, highlighting differences between algorithmic and simulation results. While all algorithms showed quick convergence, DA outperformed DFO and PSO in meeting design objectives, providing the most optimal solution for the circuit design.
Scope and Challenges of Nano-FET for Digital Circuit Design Jyoti Kandpal, Swagata Devi Nano Fet Devices Miniaturization Simulation and Applications Part 2, 2025 Over the previous thirty years, the scaling of complementary metal-oxidesemiconductor (CMOS) technology has stood crucial to the continued advancement of the silicon-based semiconductor industry. However, when technological scaling reaches the nanoscale zone, CMOS devices face several significant challenges, including higher leakage currents, difficulty increasing on-current, massive parameter changes, low yield and reliability, increased manufacturing costs, etc. In order to sustain previous advances, numerous developments in CMOS technologies and device topologies have been developed and put into practice. Simultaneously with these investigations, some innovative nanoelectronic devices, labelled as "Beyond CMOS Devices," are currently intensively investigated and developed as potential replacements or supplements for eventually scaled classic CMOS devices. Despite offering system integration at extremely high densities, these nanoelectronic devices continue to be in their infancy and confront numerous challenges, including high variations and low dependability. The actual implementation of these promising technologies necessitates substantial study at the device and system architectural levels.
Optimizing Circuit Synthesis: Integrating Neural Networks and Evolutionary Algorithms for Increased Design Efficiency Swagata Devi, Naushad Manzoor Laskar, Shreyas Nirgude, Saanvi Srivastava Advancing VLSI Through Machine Learning Innovations and Research Perspectives, 2025 Evolutionary algorithms are employed by simulation-based circuit synthesizers, which are modern tools for designing analog circuits, to determine the ideal circuit sizes. Optimizing a design by hand becomes laborious, necessitating the use of optimization techniques. The lengthy execution time brought on by the large number of simulations is one significant issue. This work advocates using neural networks, which drastically reduce the execution time, to determine circuit performance rather than simulations. The case study of a high-swing self-biased folded cascode amplifier is considered. First, the hybrid whale particle swarm optimization (HWPSO) and other bioinspired algorithms are implemented to optimize circuit performance. Later, our proposed simulation-based circuit synthesizer is employed using the data from previous generations to train artificial neural networks (ANNs) within the optimization-based iterative loops. Neural networks are next used in place of the simulator to estimate performance characteristics. The outcomes of simulations show how well HWPSO and ANN approaches compare in terms of effectively determining optimal design specifications, such as gain, power, noise, and area.
Exploring the Potential of Tunnel Field-Effect Transistors in Biomedical Devices: A Comprehensive Survey Swagata Devi, Jagritee Talukdar, Naushad Manzoor Laskar, Sagarika Choudhury IETE Journal of Research, 2025 Implantable medical devices have revolutionized healthcare by providing continuous monitoring and therapeutic interventions within the human body. The overall performance of these devices is heavily dependent on the effectiveness and efficiency of integrated electronic components, such as transistors. This survey explores the growing utilization of Tunnel Field-Effect Transistors (TFETs) in implantable devices, shedding light on their advantages and challenges in this specific application domain. TFETs, characterized by their unique tunnelling mechanism, offer several advantages that make them well suited for implantable devices. Their low-power consumption, reduced leakage current, and improved subthreshold swing make them ideal for energy-efficient, long-lasting operation within the constrained power budgets of implantable devices. Furthermore, TFETs exhibit excellent performance at low supply voltages, ensuring minimal tissue damage and heat generation. This survey also addresses the challenges associated with TFETs in implantable devices, including fabrication complexities, variability, and compatibility with existing technologies. It highlights recent advancements in TFET technology that address these concerns, such as improved material choices and manufacturing techniques. As technology continues to advance, TFETs are poised to play a pivotal role in improving the overall efficiency and reliability of life-saving technologies and medical devices. Overall, this survey provides valuable insights into the current state and future prospects of TFETs in implantable devices, guiding researchers and engineers in harnessing their potential for the benefit of healthcare and patient well-being.
Design and Analysis of OTA-OC CMOS Filter for Recording High Focal Oscillations-EEG Application Swagata Devi, Sourav Nath, Koushik Guha, Krishna Lal Baishnab Smart Electronic Devices and Systems for Biomedical and Healthcare Applications, 2025 The neural recording arrangement in a biomedical signal acquisition system records the neural activities of the brain. The electroencephalogram (EEG) signals have weak amplitude and require proper amplification for further processing. The relatively small voltage in the signals results in their high susceptibility to collecting noise from supplies, electrodes, and added sources. The analog front-end (AFE) of a neural system demands a bio amplifier that will magnify the signal at low power and low noise. Also, it is followed by a low pass filter (LPF) that will allow the specific bandwidth of the signals to pass through and reject the unwanted signals. The acceptance of low power methods lessens heat dissipation. The high amount of heat has the capability to damage the surrounding tissues, which is undesirable. One of the advantages of low power and low supply devices is that the bulk-sized battery usage can be prevented. This will increase the battery longevity and prevent the trouble of frequent substitution of battery. In this article, the focus is on the design of an OTA-C filter that will operate by consuming low power in the circuit. The analog designers face challenges in lowering the power of the circuit, 212in correspondence to its noise contribution and concerned bandwidth. These challenges are addressed in the proposed work. The low-frequency circuits necessitate huge capacitors and resistors, so they occupy a large chip area, but the design of implantable designs require less area. The OTA-C filters have gained popularity because they are fundamentally tuneable, resistor-less, and can be designed on small chips. The proposed OTA-C design is a third-order LPF and is capable of allowing only a specific range of frequencies, which belongs to the set of EEGs. These are known as high-frequency oscillations (HFOs) and are the biomarkers for the detection of neural diseases like epilepsy. The proposed filter is designed in a 180 nm SCL Cadence technology and operates at a 1.8 V. The neural amplifier achieves a mid-band gain of 54.2 dB and a −3 dB bandwidth in the range of 7.89–691 Hz.
VLSI Realization of Smart Systems Using Blockchain and Fog Computing R. Hanumantharaju, K. N. Shreenath, Sagarika Choudhury, Swagata Devi, Naushad Manzoor Laskar Advancing VLSI Through Machine Learning Innovations and Research Perspectives, 2025 Blockchain has proven to be a fascinating field of study, and many different businesses have benefited from its applications. In a similar vein, the security, privacy, secrecy, and decentralization of blockchain technology present enormous opportunities for the healthcare industry. Nevertheless, issues with data management, security, and integrity plague electronic health record (EHR) systems. This research explores how blockchain technology can revolutionize EHR systems and perhaps address these problems. This chapter offers a Very Large Scale Integration (VLSI)-based framework for implementing blockchain technology for EHR in the healthcare industry. By giving users granular access control, the proposed framework seeks to safeguard electronic record storage and apply blockchain technology to EHRs. Additionally, the approach addresses the issue of scalability that blockchain technology generally faces by utilizing off-chain record storing. This framework offers a scalable, safe, and essential blockchain-based alternative to the EHR system. Fog nodes are distributed fog-computing entities made up of one or more physical devices with processing and sensing capabilities that facilitate the deployment of fog services.
Bridging Innovation With Tunnel Field-Effect Transistors: Paving the Way for Advanced Biomedical Devices S Devi, RA Afre Convergence of Antenna Technologies, Electronics, and AI, 189-208 , 2025 2025.0
Analysis of a Low-Power OTA-Based Neural Amplifier Design for EEG Signal Acquisition S Nath, L Kundu, S Devi, K Guha, KL Baishnab Journal of Circuits, Systems and Computers 33 (10), 2450174 , 2024 2024.0 Citations: 4
A Comprehensive Review of Bio-Inspired Optimization Algorithms Including Applications in Microelectronics and Nanophotonics Z Jakšić, S Devi, O Jakšić, K Guha Biomimetics 8 (3), 278 , 2023 2023.0 Citations: 120
Design and Analysis of a Fifth Order Low Pass Gm -C Filter for Seizure Detection KLB Swagata Devi, Sourav Nath, Koushik Guha Arabian Journal for Science and Engineering , 2023 2023.0 Citations: 10
Optimized Design of a Self-Biased Amplifier for Seizure Detection Supplied by Piezoelectric Nanogenerator: Metaheuristic Algorithms versus ANN-Assisted Goal Attainment Method S Devi, K Guha, O Jakšić, KL Baishnab, Z Jakšić Micromachines 13 (7), 1104 , 2022 2022.0 Citations: 6
Design and Analysis of Various Neural Preamplifier Circuits S Devi, K Guha, KL Baishnab Sub-Micron Semiconductor Devices, 299-308 , 2022 2022.0
Survey on various architectures of preamplifiers for electroencephalogram (EEG) signal acquisition S Devi, K Guha, KL Baishnab, J Iannacci, N Krishnaswamy Microsystem Technologies 28 (4), 995-1009 , 2022 2022.0 Citations: 10
Swarm intelligence-based mono and multi-objective methods for sizing preamplifier circuits for biomedical applications S Devi, K Guha, KL Baishnab International Journal of Nanoparticles 14 (2-4), 159-180 , 2022 2022.0 Citations: 2
Energy-Efficient Hardware Implementation of K-means Clustering Algorithm S Nath, S Devi, M Loukrakpam, K Guha, KL Baishnab Micro and Nanoelectronics Devices, Circuits and Systems: Select Proceedings … , 2022 2022.0
Design of low power preamplifier IC for cochlear implant using split folded cascode technique S Nath, NM Laskar, S Devi, K Guha, KL Baishnab, J Iannacci Microsystem Technologies 27 (9), 3483-3491 , 2021 2021.0 Citations: 9
Modelling and analysis of a modified preamplifier for seizure detection S Devi, K Guha, NM Laskar, S Nath, KL Baishnab, J Iannacci, ... Microsystem Technologies 27, 3545-3558 , 2021 2021.0 Citations: 13
Metaheuristic algorithms-based approach for optimal design of improvised fully differential amplifier for biomedical applications S Devi, K Guha, KL Baishnab 2021 Devices for Integrated Circuit (DevIC), 605-609 , 2021 2021.0 Citations: 9
Design and Analysis of an Improvised Fully Differential Amplifier S Devi, K Guha, NM Laskar, S Nath, KL Baishnab Electronic Systems and Intelligent Computing: Proceedings of ESIC 2020, 899-908 , 2020 2020.0 Citations: 3
Physiological measurement platform using wireless network with Android application S Devi, S Roy Informatics in Medicine Unlocked 7, 1-13 , 2017 2017.0 Citations: 7
Informatics in Medicine Unlocked S Devi, S Roy
MOST CITED SCHOLAR PUBLICATIONS
A Comprehensive Review of Bio-Inspired Optimization Algorithms Including Applications in Microelectronics and Nanophotonics Z Jakšić, S Devi, O Jakšić, K Guha Biomimetics 8 (3), 278 , 2023 2023.0 Citations: 120
Modelling and analysis of a modified preamplifier for seizure detection S Devi, K Guha, NM Laskar, S Nath, KL Baishnab, J Iannacci, ... Microsystem Technologies 27, 3545-3558 , 2021 2021.0 Citations: 13
Design and Analysis of a Fifth Order Low Pass Gm -C Filter for Seizure Detection KLB Swagata Devi, Sourav Nath, Koushik Guha Arabian Journal for Science and Engineering , 2023 2023.0 Citations: 10
Survey on various architectures of preamplifiers for electroencephalogram (EEG) signal acquisition S Devi, K Guha, KL Baishnab, J Iannacci, N Krishnaswamy Microsystem Technologies 28 (4), 995-1009 , 2022 2022.0 Citations: 10
Design of low power preamplifier IC for cochlear implant using split folded cascode technique S Nath, NM Laskar, S Devi, K Guha, KL Baishnab, J Iannacci Microsystem Technologies 27 (9), 3483-3491 , 2021 2021.0 Citations: 9
Metaheuristic algorithms-based approach for optimal design of improvised fully differential amplifier for biomedical applications S Devi, K Guha, KL Baishnab 2021 Devices for Integrated Circuit (DevIC), 605-609 , 2021 2021.0 Citations: 9
Physiological measurement platform using wireless network with Android application S Devi, S Roy Informatics in Medicine Unlocked 7, 1-13 , 2017 2017.0 Citations: 7
Optimized Design of a Self-Biased Amplifier for Seizure Detection Supplied by Piezoelectric Nanogenerator: Metaheuristic Algorithms versus ANN-Assisted Goal Attainment Method S Devi, K Guha, O Jakšić, KL Baishnab, Z Jakšić Micromachines 13 (7), 1104 , 2022 2022.0 Citations: 6
Analysis of a Low-Power OTA-Based Neural Amplifier Design for EEG Signal Acquisition S Nath, L Kundu, S Devi, K Guha, KL Baishnab Journal of Circuits, Systems and Computers 33 (10), 2450174 , 2024 2024.0 Citations: 4
Design and Analysis of an Improvised Fully Differential Amplifier S Devi, K Guha, NM Laskar, S Nath, KL Baishnab Electronic Systems and Intelligent Computing: Proceedings of ESIC 2020, 899-908 , 2020 2020.0 Citations: 3
Swarm intelligence-based mono and multi-objective methods for sizing preamplifier circuits for biomedical applications S Devi, K Guha, KL Baishnab International Journal of Nanoparticles 14 (2-4), 159-180 , 2022 2022.0 Citations: 2
Bridging Innovation With Tunnel Field-Effect Transistors: Paving the Way for Advanced Biomedical Devices S Devi, RA Afre Convergence of Antenna Technologies, Electronics, and AI, 189-208 , 2025 2025.0
Design and Analysis of Various Neural Preamplifier Circuits S Devi, K Guha, KL Baishnab Sub-Micron Semiconductor Devices, 299-308 , 2022 2022.0
Energy-Efficient Hardware Implementation of K-means Clustering Algorithm S Nath, S Devi, M Loukrakpam, K Guha, KL Baishnab Micro and Nanoelectronics Devices, Circuits and Systems: Select Proceedings … , 2022 2022.0