Dr. Soumen Mallick
@bcrec.ac.in
Assistant Professor (Grade-II)
Dr. B. C. Roy Engineering College, Durgapur
Scopus Publications
Scholar Citations
Scholar h-index
Scholar i10-index
Scopus Publications
Soumen Mallick, Rajib Kar, and Durbadal Mandal
Inderscience Publishers
S. Mallick, R. Kar, D. Mandal, Tanya Dasgupta, and S. P. Ghoshal
Springer Singapore
This paper presents in front of us a novel approach for the optimal design of a Low Noise Amplifier (LNA) with inductive source degeneration circuit using a recently proposed evolutionary optimization technique called PSO with Aging Leader and Challenger (ALC-PSO). The proposed ALC-PSO based approach has succeeded in dealing with the disadvantages faced by PSO algorithm and is employed in this paper for the optimal design of LNA circuit. The MOSFET widths and component’s values are optimized by using ALC-PSO algorithm in order to maximize the gain, minimize the Noise Figure (NF) and to optimize the overall performance of the LNA circuit. The simulation results obtained for the designed LNA circuit confirm the effectiveness of the ALC-PSO based approach over PSO in terms of solution quality, design specifications, and design objectives. The optimally implemented LNA circuit in 0.35 µm CMOS technology yields the gain of 18.64 dB, noise figure of 1.779 dB and power dissipation of 10.60 mW.
S. Mallick, J. R. Akhil, A. Dasgupta, Rajib Kar, Durbadal Mandal, and Sakti Prasad Ghoshal
IEEE
This paper presents a novel approach for the optimal design of a Low Noise Amplifier (LNA) with inductive source degeneration circuit using a novel hybrid optimization technique called fitness based adaptive differential evolution with particle swarm optimization (ADEPSO). The simulation results obtained for the designed LNA confirm the effectiveness of the ADEPSO based approach over PSO in terms of the solution quality, design specifications and design objectives. The optimally designed CMOS LNA circuit implemented in 0.18 μm CMOS technology yields a gain of 22.11 dB and the noise figure of 0.799 dB and the power dissipation of 6.6 mW.
Soumen Mallick, Kumari Suman, Rajib Kar, Durbadal Mandal, and Sakti Prasad Ghoshal
IEEE
An optimally designed CMOS Op-Amp has been presented in this article. Opposition concept based harmony Search (OHS) algorithm is applied for obtaining the minimum MOS area of the proposed Op-Amp. The proposed OHS based analog CMOS Op-Amp circuit design has alleviated from the problems of suboptimal convergence and stagnation, unlike Particle Swarm Optimization (PSO) and Harmony Search (HS). The least total MOS area of 121.8 μm2 is obtained in 0.35 μm CMOS technology with a power dissipation of 616.3 μW.
S. Mallick, R. Kar, D. Mandal, and S. P. Ghoshal
Springer Science and Business Media LLC
In this paper, a hybrid population based meta-heuristic search algorithm named as gravitational search algorithm (GSA) combined with particle swarm optimization (PSO) (GSA–PSO) is proposed for the optimal designs of two commonly used analog circuits, namely, complementary metal oxide semiconductor (CMOS) differential amplifier circuit with current mirror load and CMOS two-stage operational amplifier circuit. PSO and GSA are simple, population based robust evolutionary algorithms but have the problem of suboptimality, individually. The proposed GSA–PSO based approach has overcome this disadvantage faced by both the PSO and the GSA algorithms and is employed in this paper for the optimal designs of two amplifier circuits. The transistors’ sizes are optimized using GSA–PSO in order to minimize the areas occupied by the circuits and to improve the design/performance parameters of the circuits. Various design specifications/performance parameters are optimized to optimize the transistor’s sizes and some other design parameters using GSA–PSO. By using the optimal transistor sizes, Simulation Program with Integrated Circuit Emphasis simulation has been carried out in order to show the performance parameters. The simulation results justify the superiority of GSA–PSO over differential evolution, harmony search, artificial bee colony and PSO in terms of convergence speed, design specifications and performance parameters of the optimal design of the analog CMOS amplifier circuits. It is shown that GSA–PSO based design technique for each amplifier circuit yields the least MOS area, and each designed circuit is shown to have the best performance parameters like gain, power dissipation etc., as compared with those of other recently reported literature. Still the difficulties and challenges faced in this work are proper tuning of control parameters of the algorithms GSA and PSO, some conflicting design/performance parameters and design specifications, which have been partially overcome by repeated manual tuning. Multi-objective optimization may be the proper alternative way to overcome the above difficulties.
Soumen Mallick, Rajib Kar, Sakti Prasad Ghoshal, and Durbadal Mandal
Inderscience Publishers
S. Mallick, K. Sudhakar, R. Kar, D. Mandal, and S. P. Ghoshal
IEEE
An optimum design of analog CMOS differential amplifier (Diff-Amp) with current mirror load has been presented in this paper. An evolutionary optimization technique called Opposition based Harmony Search Algorithm (OHS) is employed to minimize the total MOSFET area of the designed circuit. The novel Harmony Search (HS) algorithm is selected as the parent and the opposition based approach is employed to it with an intention to exhibit accelerated near-global convergence profile. At the initialization stage, for choosing the randomly generated population/solutions, opposite solutions are also considered and the fitter one is selected as apriori guess. This causes faster convergence profile. Each solution in Harmony Memory (HM) is generated on the basis of memory consideration rule, a pitch adjustment rule and a re-initialization process which gives the optimum result corresponding to the least error fitness in multidimensional search space. Differential Evolution (DE), Harmony Search (HS), Artificial Bee Colony (ABC) and Particle Swarm Optimization (PSO) have an inbuilt disadvantage of early convergence and stagnation problem. But in OHS optimization technique has overcome these shortcomings. The optimally designed differential amplifier circuit occupies the least total MOS area, and shows the best design conditions like gain, power dissipation etc., in comparison with the formerly reported literature.
S. Mallick, R. Kar, S. P. Ghoshal, and D. Mandal
Wiley
This paper presents the optimal designs of two analogue complementary metal-oxide-semiconductor CMOS amplifier circuits, namely differential amplifier with current mirror load and two-stage operational amplifier. A modified Particle Swarm Optimization PSO, called Craziness-based Particle Swarm Optimization CRPSO technique is applied to minimize the total MOS area of the designed circuits. CRPSO is a highly modified version of conventional PSO, which adopts a number of random variables and has a better and faster exploration and exploitation capability in the multidimensional search space. Integration of craziness factor in the fundamental velocity term of PSO not only brings diversity in particles but also pledges convergence close to global best solution. The proposed CRPSO-based circuit optimization technique is reassured to be free from the intrinsic disadvantages of premature convergence and stagnation, unlike Differential Evolution DE, Harmony Search HS, Artificial Bee Colony ABC and Particle Swarm Optimization PSO. The simulation results achieved for the two analogue CMOS amplifier circuits establish the efficacy of the proposed CRPSO-based approach over those of DE, HS, ABC and PSO in terms of convergence haste, design conditions and design goals. The optimally designed analogue CMOS amplifier circuits occupy the least MOS area and show the best performance parameters like gain and power dissipation, in compared with the other reported literature. Copyright © 2016 John Wiley & Sons, Ltd.
S. Mallick, R. Kar, D. Mandal, and S.P. Ghoshal
Informa UK Limited
This paper proposes a novel hybrid optimisation algorithm which combines the recently proposed evolutionary algorithm Backtracking Search Algorithm (BSA) with another widely accepted evolutionary algorithm, namely, Differential Evolution (DE). The proposed algorithm called BSA-DE is employed for the optimal designs of two commonly used analogue circuits, namely Complementary Metal Oxide Semiconductor (CMOS) differential amplifier circuit with current mirror load and CMOS two-stage operational amplifier (op-amp) circuit. BSA has a simple structure that is effective, fast and capable of solving multimodal problems. DE is a stochastic, population-based heuristic approach, having the capability to solve global optimisation problems. In this paper, the transistors’ sizes are optimised using the proposed BSA-DE to minimise the areas occupied by the circuits and to improve the performances of the circuits. The simulation results justify the superiority of BSA-DE in global convergence properties and fine tuning ability, and prove it to be a promising candidate for the optimal design of the analogue CMOS amplifier circuits. The simulation results obtained for both the amplifier circuits prove the effectiveness of the proposed BSA-DE-based approach over DE, harmony search (HS), artificial bee colony (ABC) and PSO in terms of convergence speed, design specifications and design parameters of the optimal design of the analogue CMOS amplifier circuits. It is shown that BSA-DE-based design technique for each amplifier circuit yields the least MOS transistor area, and each designed circuit is shown to have the best performance parameters such as gain, power dissipation, etc., as compared with those of other recently reported literature.