USHA BHANU NAGESWARAN
@srmvalliammai.ac.in
Professor , Department of ECE
SRM Valliammai Engineering College
EDUCATION
B.E ECE
M.E VLSI Design
Ph. D in VLSI Signal Processing
RESEARCH, TEACHING, or OTHER INTERESTS
Electrical and Electronic Engineering, Hardware and Architecture, Signal Processing, Computer Vision and Pattern Recognition
Scopus Publications
Scholar Citations
Scholar h-index
Scholar i10-index
Scopus Publications
Saravanakumar Chandrasekaran and Usha Bhanu Nageswaran
Springer Science and Business Media LLC
Saravanakumar C, Usha Bhanu N, Subhashini N, Sureshkumar V, Marirajan S, and Sandhya V P
IEEE
For quantitative single-cell biology using optical microscopy, locating cells in a microscopic image is critical. Although there are several segmentation methods available, successful segmentation is difficult and typically necessitates problem-specific algorithm tweaking. Furthermore, recent algorithms are dependent on a few fundamental methodologies that detect cell borders using the image's gradient field. Many microscopy procedures, on the other hand, can provide pictures with distinct intensity patterns at the cell membrane. This has yet to be leveraged algorithmically to develop more generic segmentation approaches. In the proposed work, a simple algorithm is employed to identify the boundary of a cell in a microscopic image and it is deployed in a hardware chip to experiment with it. The results show the isolation of boundaries of the cell with improvement in the area occupied by the hardware. The resource-sharing technique is employed to reduce the area by 50 - 60% without compromising the identification of the boundary of the cell in the microscopic image.
N Usha Bhanu and C Saravanakumar
IEEE
The growing demand of high-resolution video on portable devices, the applications require higher coding efficiency, high throughput and low power for handling heterogenous types of video signals. This paper presents a survey on possibility of applying Machine Learning (ML) models in H.265/ HEVC video encoder unit. Higher computational complexity with respect to motion estimation, coding, and parallel processing architectures are required for HEVC. The existing HEVC algorithms are based on spatial temporal relationship which requires dynamic video sequences handling for fast changes in scenes. This paper focuses on the possible realization of machine learning algorithms for Rate Control (RC) in video sequences, Coding Unit (CU) depth decision, Neural network-based Motion Estimation and Compensation, adaptive de-blocking filter for reducing blocking artifacts and task driven semantic coding for real time video applications. The algorithms are surveyed with respect to the learning process used in various units of HEVC encoders and summarized in terms of parameters achieved and datasets used in the existing literature.
Benila S Benila S and Usha Bhanu N. Benila S
Angle Publishing Co., Ltd.
<p>In Internet of things enabled healthcare system, sensors create vast volumes of data that are analyzed in the cloud. Transferring data from the cloud to the application takes a long time. An effective infrastructure can reduce latency and costs by processing data in real-time and close to the user devices. Fog computing can solve this issue by reducing latency by storing, processing, and analyzing patient data at the network edge. Placing the resources at fog layer and scheduling tasks is quite challenging in Fog computing. This paper proposes a Fog Managed Data Model (FMDM) with three layers namely Sensor, Fog and cloud to solve the aforementioned issue. Sensors generate patient data and that are managed and processed by Fog and cloud layers. Tasks are scheduled using a Weighted Fog Priority Job Scheduling algorithm (WFPJS) and fog nodes are allocated based on Priority based Virtual Machine Classification Algorithm (PVCA). The performance of this model is validated with static scheduling techniques with variable patient counts and network configurations. The proposed FMDM with WFPJS reduces response time, total execution cost, network usage, network latency, computational latency and energy consumption.</p> <p>&nbsp;</p>
C Saravanakumar and N Usha Bhanu
IEEE
One of the major issues in the Bioinformatics discipline is to construct a method by which the precise protein-coding region can be identified in the intended nucleotide series. The exact spotting of protein coding regions in a nucleotide is valuable in numerous entities. For an instance, it aids in describing unique proteins, develop drugs, and furthermore in uncovering the developmental foundation of a specific living being. Digital Signal Processing (DSP) rooted technique is quite popular for identifying protein coding regions. The main fundamental stage of the DSP oriented prediction of exon, is to direct the nucleotide base to the numeric values. Choosing a numerical mapping configuration influences the characteristics of the DNA sequence, helping them to pinpoint the precise area of the exon. Over the most recent twenty years, a number of methods to map the nucleotides have been effectively utilized as a preprocessing stage for exon prediction. The proposed method of mapping a sequence outerforms other schemes in predicting the region of exons.
S. Benila and N. Usha Bhanu
Computers, Materials and Continua (Tech Science Press)
Saravanakumar C and Usha Bhanu N
IEEE
This work deeply studies the identification of stuck at faults and its corresponding test vectors for a circuit. The circuit under consideration is a 2 – to – 1 multiplexer designed by NAND gate developed with the FinFET technology. The main constraint on design of the circuit is its area and power consumption. The design is simulated and its functionality is verified using Microwind 3.8. The simulation of PODEM algorithm for the designed circuit is proposed in this paper. The netlist generated from this simulation is adapted to simulate the PODEM algorithm to detect the faults. The simulation is carried out in MATLAB2019b and identified the fault location with a input test vector.
Vani Rajamanickam, Ushabhanu Nageswaran, and Sangeetha Marikkannan
Agora University of Oradea
The objective of the paper is to develop new block matching Motion Estimation (ME) algorithm using hybrid search patterns along the direction of best match. The search efficiency for sequences with fast motions and high resolutions is improved by proposing New Cross Diagonal-Hexagon Search (NCDHS) algorithm which involves a novel multi half-hexagon grid global search pattern and a cross diagonal-hexagon local search pattern. The new search pattern enables the proposed algorithm to perform better search using 9.068 search points on an average, to obtain optimal motion vector with slight improvement in quality. This inturn reduces ME Time upto 50.11%, 47.12%, 32.99% and 43.28% on average when compared to the existing Diamond Search (DS), Hexagon Search (HS), New Cross Hexagon Search (NHEXS) and Enhanced Diamond Search (EDS) algorithms respectively. The novelty of the algorithm is further achieved by applying the algorithm proposed for live streaming application. The NCDHS algorithm is run on two MATLAB sessions on the same computer by establishing the connection using Transmission Control Protocol (TCP) /Internet Protocol (IP) network. The ME Time obtained is 14.5986 seconds for a block size 16x16, is less when compared to existing algorithms and that makes the NCDHS algorithm suitable for real time streaming application.
W. L. Nancy Priyanka and N. Usha Bhanu
IEEE
Cognitive radio networks are the next generation networks that are designed for the efficient utilization of the available spectrum. Cognitive radios are capable of changing their transmission parameters according to the sensed environment thereby avoiding interference between the cognitive users. In cognitive radio sensor networks the sudden appearance of a primary user or a failure in the node or a link affects the network performance of a secondary user the route discovery process has to be repeated by the secondary user which increases the delay in the packet delivery to the destination node. Hence this paper includes the comparison of two efficient routing algorithms called backup routing algorithm and dynamic path switching routing algorithm. The performance of the two routing algorithms are analysed and compared terms of packet delivery ratio (PDR), throughput and delay. The PDR for backup routing is 91%. The delay for backup routing is 400μs. The throughput is 206bps for backup routing algorithm.
N. Usha Bhanu and A. Chilambuchelvan
Inderscience Publishers
The inherent advantage of the in-place computation of the lifting-based discrete wavelet transform over the convolutional method makes it suitable for efficient hardware implementation with lower computational complexity. A high speed line-based direct mapped architecture for the lifting-based discrete wavelet of an image is proposed in this paper. Clock gating is used to reduce the switching activity of multipliers in the idle state for low power implementation of the lifting DWT. The comparison of the direct mapped and folded architectures is presented, in terms of speed and hardware requirements. The whole architecture is optimised to achieve better speed up and higher hardware utilisation by using a single clock for the predict and update operations. The speed performance of the folded architecture is limited by the critical path delay. The lifting algorithm is coded in MATLAB and implemented using Altera Cyclone II FPGA. The results obtained show that the hardware implementation of the lifting algorithm outperforms with respect to its software counterpart, achieving a high speed of 260 MHz, which is suitable for low power embedded multimedia applications.
N. Usha Bhanu and A. Chilambuchelvan
Springer Science and Business Media LLC
Usha Bhanu Nageswaran and A. Chilambuchelvan
ACM
Evaluating the previous work is an important part of developing new hardware efficient methods for the implementation of DWT through Lifting schemes. The aim of this paper is to give a review of VLSI architectures for efficient hardware implementation of wavelet lifting schemes. The inherent in place computation of lifting scheme has many advantages over conventional convolution based DWT. The architectures are represented in terms of parallel filter, row column, folded, flipping and recursive structures. The methods for scanning of images are the line-based and the block-based and their characteristics for the given application are given. The various 1D and 2D architectures are analyzed in terms of hardware and timing complexity involved with the given size of input image and required levels of decomposition. This study is useful for deriving an efficient method for improving the speed and hardware complexities of existing architectures and to design a new hardware implementation of multilevel DWT using lifting schemes.
Usha Bhanu Nageswaran and A. Chilambuchelvan
ACM
Efficient line based hardware architecture for the lifting based discrete wavelet of an image is proposed in this work. Lifting Scheme reduces the number of operations execution steps to almost one-half of those needed with a conventional convolution approach. Performance comparison of simulation results for lifting DWT using MATLAB and VHDL is done to verify the proper functionality of the developed module. The comparison of direct mapped and folded VLSI architectures for lifting schemes is presented in terms of speed and hardware requirements. The whole architecture is being optimized to achieve better speed up and higher hardware utilization by using a single clock for predict and update operation. The proposed architecture is implemented in Xilinx Spartan 3E FPGA. The data flow of the proposed architecture is regular, simple, control complexity and achieves 100% hardware utilization. The entire system runs at faster rate and reaches a speed performance suitable for real time stand-alone image/video applications.