Arish Sateesan

@kuleuven.be

PhD student, ESAT
KU Leuven



                    

http://researchid.co/arishs

RESEARCH INTERESTS

Embedded System Security, FPGA Based System Design, Convolutional Neural Networks

17

Google Scholar Citations

3

Google Scholar h-index

RECENT SCHOLAR PUBLICATIONS

  • Optimization of Convolutional Neural Networks on Resource Constrained Devices
    S Arish, S Sharad, KG Smitha
    2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2019

  • Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA
    S Arish, RK Sharma
    Springer US (CSSP) - International Journal of Circuits, Systems, and Signal 2017

  • An efficient binary multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm
    S Arish, RK Sharma
    IEEE - Communication Technologies (GCCT), 2015 Global Conference on, 192-196 2015

  • An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm
    S Arish, RK Sharma
    IEEE - 2015 International Conference on Signal Processing and Communication 2015

  • Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications
    S Arish, RK Sharma
    IEEE - Signal Processing and Integrated Networks (SPIN), 2015 2nd 2015

MOST CITED SCHOLAR PUBLICATIONS

  • An efficient binary multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm
    S Arish, RK Sharma
    IEEE - Communication Technologies (GCCT), 2015 Global Conference on, 192-196 2015
    Citations: 7

  • An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm
    S Arish, RK Sharma
    IEEE - 2015 International Conference on Signal Processing and Communication 2015
    Citations: 5

  • Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications
    S Arish, RK Sharma
    IEEE - Signal Processing and Integrated Networks (SPIN), 2015 2nd 2015
    Citations: 5