Ivan Saraiva Silva holds a Bachelor's degree in Electrical Engineering (1989) and a Master's degree in Electrical Engineering (1990) from the Federal University of Paraíba. He earned a Diplôme dÉtudes Approfondies (DEA) in Microelectronics and Microinformatics from Pierre and Marie Curie University (Paris VI) in 1991, and a Ph.D. in Computer Science from the same institution in 1995. From 1996 to 2009, he was a faculty member in the Department of Informatics and Applied Mathematics at the Federal University of Rio Grande do Norte. He is currently a Full Professor in the Department of Computer Science at the Federal University of Piauí. His research interests lie in the field of Computer Science, with an emphasis on Integrated System Design, particularly in the areas of Hardware Accelerator Microarchitecture, Reconfigurable Architectures, Computer Vision Applications, Smart Cities, Vehicular Embedded Systems, and Urban Mobility.
RESEARCH, TEACHING, or OTHER INTERESTS
Hardware and Architecture, Computer Vision and Pattern Recognition, Electrical and Electronic Engineering
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Scopus Publications
Scopus Publications
Feasibility-Aware Design-Space Exploration of Transparent Coarse-Grained Reconfigurable Architectures Thiago R. B. S. Soares, Ivan S. Silva Electronics Switzerland, 2026 Coarse-Grained Reconfigurable Architectures (CGRAs) execute compute-intensive kernels on a reconfigurable processing mesh. Transparent CGRAs extend this model by generating configurations at runtime and storing them in a dedicated cache, removing compiler dependence and enabling adaptive behavior. Although prior work has explored mapping strategies and mesh scaling, the feasibility of the configuration cache remains unaddressed, as it is commonly treated as a generic storage block. This paper presents a feasibility study of configuration cache organizations and a design-space exploration of Transparent CGRAs, introducing a parameterized cache geometry model that relates cache parameters to the processing mesh and configuration structure. The model enables realistic estimates of area, latency, and energy at the digital system level and is applied to three Transparent CGRAs from the literature and five additional designs covering a wide range of spatial and temporal organizations. The results show that mesh scaling must be balanced with cache feasibility: wide I/O paths and large configurations lead to impractical caches, whereas well-proportioned meshes achieve competitive performance with modest overheads. Under the proposed exploration, selected expanded meshes outperform a two-issue out-of-order processor by up to 1.4× while increasing area by only 14.8% and energy by 2%. These findings demonstrate that Transparent CGRAs are viable, but their scalability depends on a realistic configuration cache design. The proposed parameterized cache model provides a structured and reproducible basis for analyzing transparency overheads and guiding future CGRA designs.
Energy-Efficient Mappings in the Athena CGRA Francisco Júnior, Ricardo Jacobi, Ivan Saraiva Silva 2026 IEEE 17th Latin American Symposium on Circuits and Systems Lascas 2026 Proceedings, 2026
Optimized method for locating the source of voltage sags Jose Carlos Filho, Fabbio Anderson da Silva Borges, Ricardo de Andrade Lira Rabelo, Ivan Saraiva Silva, Antonio Oseas de Carvalho Filho Journal of Communications Software and Systems, 2021
UVMP: Virtualizable multi-core platform Ivan Saraiva Silva, Ramon Nepomuceno, Tackyss Mafuta, Eeugenio S. Carvalho 38th Latin America Conference on Informatics Clei 2012 Conference Proceedings, 2012
DDR SDRAM memory controller for digital TV decoders Hadley M. Siqueira, Ivan S. Silva, Marcio E. Kreutz, Edgard F. Correa Proceedings 2011 Brazilian Symposium on Computing System Engineering Sbesc 2011, 2011
Exploring memory organization in virtual MP-SoC platforms Bruno Cruz Oliveira, Márcio Eduardo Kreutz, Edgard de Faria Corrêa, Ivan Saraiva Silva Sbcci 10 Proceedings of the 23rd Symposium on Integrated Circuits and Systems Design, 2010
Using NoC routers as processing elements Sílvio Fernandes, Bruno C. Oliveira, Ivan Saraiva Silva Proceedings of the 22nd Symposium on Integrated Circuits and Systems Design Sbcci 2009, 2009
RoSA: A reconfigurable stream-based architecture Monica Magalhaes Pereira, Bruno Cruz de Oliveira, Ivan Saraiva Silva Proceedings Sbcci 2007 20th Symposium on Integrated Circuits and System Design, 2007
High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard Proceedings IEEE International Symposium on Circuits and Systems, 2006
Papílio cryptography algorithm Frederiko Stenio de Araújo, Karla Darlene Nempomuceno Ramos, Benjamín René Callejas Bedregal, Ivan Saraiva Silva Lecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics, 2004
