James Garland

@tcd.ie

PhD Candidate at the School of Computer Science and Statistics
Trinity College Dublin



                             

https://researchid.co/jpgarland

An Irish Brummie with the lilt but not the brogue of the Irish

EDUCATION

MSc System Design (Microelectronics)

RESEARCH INTERESTS

Microarchitectural optimisations of machine learning algorithms in hardware, FPGA and ASIC.

121

Scholar Citations

4

Scholar h-index

4

Scholar i10-index

RECENT SCHOLAR PUBLICATIONS

  • Spatial Mapping of light aircraft with stereo-vision camera for use on Unmanned Aircraft System for defect localisation
    L Connolly, D O’Gorman, J Garland, EF Tobin
    2023 International Conference on Unmanned Aircraft Systems (ICUAS), 413-418 2023

  • Feature Representation in Pretrained Deep Metric Embeddings
    R Furlong, V O'Brien, J Garland, DP Alonso, FD Mateos
     2023

  • Laser Beam Propagation Features via Atmospheric Turbulence-Induced Beam Wander: Testbed Conceptual Design
    HM Al Juboori, J Garland
    COAT-2023-workshop (Communications and Observations through Atmospheric 2023

  • Laser Beam Propagation Features via Atmospheric Turbulence-Induced Beam Wander: Testbed Conceptual Design
    JG Haider M Al Juboori
    COAT-2023-workshop (Communications and Observations through Atmospheric 2023

  • HOBFLOPS for CNNs: Hardware Optimized Bitslice Parallel Floating-Point Operations for Convolutional Neural Networks
    J Garland, D Gregg
    Research Square 2021

  • Low-precision Logarithmic Number Systems: Beyond Base-2
    DG Syed Asad Alam, James Garland
    ACM Transactions on Architecture and Code Optimization 18 (4), 1-25 2021

  • Feature Representation in Deep Metric Embeddings
    R Furlong, V O'Brien, J Garland, D Palacios-Alonso, F Dominguez-Mateos
    arXiv preprint arXiv:2102.03176 2021

  • Arbitrary Precision and Low Complexity Micro-Architectural Arithmetic Optimisations of Machine Learning Algorithms for Compute Bound and High-Performance Systems
    JP Garland
    Trinity College Dublin 2021

  • Metric Embedding Sub-discrimination Study.
    R Furlong, V O'Brien, J Garland, F Domnguez-Mateos
    CoRR 2021

  • 6 Hardware and software performance in deep learning
    A Anderson, J Garland, Y Wen, B Barabasz, K Persand, A Vasudevan, ...
    Many-Core Computing: Hardware and Software, 141-165 2019

  • Low Complexity Multiply-Accumulate Units for Convolutional Neural Networks with Weight-Sharing
    J Garland, D Gregg
    ACM Transactions on Architecture and Code Optimization (TACO) 15 (3), 31:1-31:24 2018

  • Low Complexity Multiply Accumulate Unit for Weight-Sharing Convolutional Neural Networks
    J Garland, D Gregg
    ACACES 2017 Poster Abstracts, 53-56 2017

  • Low complexity multiply accumulate unit for weight-sharing convolutional neural networks
    J Garland, D Gregg
    IEEE Computer Architecture Letters 16 (2), 132-135 2017

  • A delay and disruption tolerant transport layer protocol
    S Farrell
    Trinity College Dublin 2008

  • Are you looking at me?
    E Meehan
     2006

  • Ltp-t: A generic delay tolerant transport protocol
    S Farrell, V Cahill
    Trinity College, Dublin, Ireland, Tech. Rep 2005

  • 2017 Index IEEE Computer Architecture Letters Vol. 16
    N Abu-Ghazaleh, A Adileh, A Agrawal, H Ahmadvand, JH Ahn, ...

MOST CITED SCHOLAR PUBLICATIONS

  • Low complexity multiply accumulate unit for weight-sharing convolutional neural networks
    J Garland, D Gregg
    IEEE Computer Architecture Letters 16 (2), 132-135 2017
    Citations: 39

  • Low Complexity Multiply-Accumulate Units for Convolutional Neural Networks with Weight-Sharing
    J Garland, D Gregg
    ACM Transactions on Architecture and Code Optimization (TACO) 15 (3), 31:1-31:24 2018
    Citations: 36

  • Ltp-t: A generic delay tolerant transport protocol
    S Farrell, V Cahill
    Trinity College, Dublin, Ireland, Tech. Rep 2005
    Citations: 27

  • Low-precision Logarithmic Number Systems: Beyond Base-2
    DG Syed Asad Alam, James Garland
    ACM Transactions on Architecture and Code Optimization 18 (4), 1-25 2021
    Citations: 11

  • A delay and disruption tolerant transport layer protocol
    S Farrell
    Trinity College Dublin 2008
    Citations: 4

  • 6 Hardware and software performance in deep learning
    A Anderson, J Garland, Y Wen, B Barabasz, K Persand, A Vasudevan, ...
    Many-Core Computing: Hardware and Software, 141-165 2019
    Citations: 3

  • HOBFLOPS for CNNs: Hardware Optimized Bitslice Parallel Floating-Point Operations for Convolutional Neural Networks
    J Garland, D Gregg
    Research Square 2021
    Citations: 1

GRANT DETAILS

Data-centric ultra-low power embedded computing
Science Foundation Ireland (Dublin)2013-04-01 to 2017-03-31
GRANT_NUMBER: 12/IA/1381