Dr Niraj Kumar Dewangan
Verified @gmail.com
Assistant Professor
Doctor of Philosophy
Currently, He is working as an Assistant Professor at the Dept. of Electrical engineering in NIT Raipur. He has published over 10+ articles/papers in various refereed national/international conferences and journals and serving as a reviewer of several journals (IET PE, IEEE PE, IEEE JESTPE, and Wiley ITEES). His research fields of interest are multilevel inverters, fault tolerance in multilevel inverters, reduced Device Count MLIs, switched capacitor MLIs, power electronics for renewable energy, real-time controllers for power electronic systems, and modulation strategies for power converters, electric vehicles, optimization techniques.
EDUCATION
Niraj Kumar Dewangan was born in India in 1986. He received B. Tech degree in Electronics and Telecommunication from B.P.U.T, Odisha, in 2008. M.Tech in Digital Communication from R.G.P.V, Bhopal, in 2014. Obtained Ph.D. degree in Department of Electrical Engineering, National Institute of Technology, Raipur in 2020. From 2008 to 2012, he was working as Lecturer at the Department of Electronics and Communication Engineering, Sagar Institute of Science and Technology-R (SISTec-R) Bhopal, India.
RESEARCH INTERESTS
Multilevel inverters, fault tolerance in multilevel inverters, reduced Device Count MLIs, switched capacitor MLIs, power electronics for renewable energy, real-time controllers for power electronic systems, and modulation strategies for power converters, electric vehicles, optimization techniques.
Scopus Publications
Scholar Citations
Scholar h-index
Scholar i10-index
Scopus Publications
Abhishek Jha, Dhruv Ray, Devesh Umesh Sarkar, Tapan Prakash, and Niraj Kumar Dewangan
Wiley
AbstractPower oscillations in modern power grids are inherent phenomena that may threaten system reliability. Therefore, to ensure acceptable system reliability, effective damping of power oscillations is inevitably required. In this context, this article introduces a novel approach to designing fractional power system stabilizer (FPSS) for effective damping of power oscillations. Bidirectional long‐short‐term memory (Bi‐LSTM) approach is adopted to predict the parameters of FPSS. The conventional phase compensation technique is used to train Bi‐LSTM network. To validate the efficacy of FPSS, different test scenarios of contingent operating conditions are simulated for the system. Comparative analysis is carried out with conventional power system stabilizers (PSSs) and optimization‐based PSS techniques. Additionally, a test scenario is performed against existing deep neural network‐based PSS methods to ascertain the robustness of the proposed PSS. Furthermore, the performance of the proposed Bi‐LSTM‐based FPSS is validated in real‐time simulation using an interfaced OPAL‐RT OP5700 hardware device.
Kasinath Jena, Krishna Kumar Gupta, Dhananjay Kumar, Niraj Kumar Dewangan, and Subash Ranjan Kabat
Springer Science and Business Media LLC
Dhananjay Kumar, Kasinath Jena, Jitendra Kumar Tandekar, Niraj Kumar Dewangan, and Vishal Rathore
Wiley
Dhananjay Kumar, Kasinath Jena, Jitendra Kumar Tandekar, Niraj Kumar Dewangan, and Vishal Rathore
Wiley
Niraj Kumar Dewangan, Deepak Verma, Rakeshwri Agrawal, Dhananjay Kumar, and Krishna Kumar Gupta
Springer Science and Business Media LLC
AbstractSafety–critical applications rely heavily on multilevel inverters. This article introduces a fault tolerant (FT) multilevel inverter sustaining an uninterrupted operation with an open switch fault occurred in a single and multiple power switches. Power semiconductor devices used in dc-ac converters increased in numbers to obtain high-quality voltage waveform which makes them vulnerable to failure. As a result, reliability is one of the biggest challenges in the utilization of multilevel inverters (MLIs) in many industrial applications. At the same time, reduced component multilevel inverters can achieve the highest resolution in output voltage waveform by compromising significant features (such as fault tolerance ability, charge balance control, etc.) but it is required to be preserved. For effective fault tolerant operation of MLIs, redundant switching states have given the highest priority in terms of switch level failures. A study is being undertaken to develop a novel fault-tolerant MLI, in the event of an open circuit fault on single and multiple switches. Therefore, the proposed FT-MLI structure can fulfill the operational requirement for a time being and claimed to be reduced components. A valid fault tolerant switching technique along with appropriate fault clearance is employed to obtain the desirable output voltage waveforms. In order to determine the feasibility of FT-MLI, performance evaluations are carried out based on results obtained under normal and abnormal operating conditions through the use of a laboratory prototype.
Niraj Kumar Dewangan, Krishna Kumar Gupta, and Mandeep Singh
IEEE
Multilevel inverters (MLIs) are growing as a potential solution for DC to AC power conversion. This work describes the design and implementation of a single-phase newly developed multilevel inverter configuration that combines a cross connected sources (CCS) based MLI and a half-bridge inverter with considerable decrease in component count for a large number of output voltage levels. The level-increment circuit (LIC) is a type of half-bridge inverter that boosts the output voltage levels in the CCS-MLI topology by nearly twice. The aforesaid approach minimises the amount of power switching devices utilised compared to conventional topologies, resulting in higher output voltage levels by minimising the THD and dv/dt stress on the load. The proposed configuration can be designed to operate in both symmetrical and asymmetrical source patterns. Symmetrical arrangement allows for the formation of four more levels in each sequence with addition of each pair of switches to the basic module. The concept has been studied using MATLAB/Simulink and a laboratory prototype.
Kasinath Jena, Niraj Kumar Dewangan, R.P. Gupta, and Dhananjay Kumar
IEEE
This study proposes a single-phase switched-capacitor (SC) topology that eliminates the need for a transformer and incorporates a shared ground. The topology utilizes eleven switches, one diode, and three capacitors to generate a nine-level waveform. The key attributes of the proposed design include zero leakage current (LC), voltage boosting capability, reduced voltage stress, and self-balancing of capacitor voltage. Furthermore, there is no need for extra balancing circuits or sensors to ensure the equilibrium of capacitor voltages. A comprehensive examination of the circuit description and operating principle has also been conducted. Through a concise comparison, the proposed topology has been shown to outperform existing alternatives in terms of component count, voltage stress, and gain. The utilization of the simulation environment ensures the accuracy of the theoretical concept.
Yadvendra Singh, Shakti Singh, Pallavee Bhatnagar, Meena Malik, Niraj K Dewangan, and Krishna Kumar Gupta
IEEE
Power electronics is an emerging and rapidly advancing technology within the realm of electrical engineering, finding wide-ranging applications in areas such as renewable energy, electric vehicles, and industrial automation. This paper aims to provide an in-depth exploration of the tools employed for comprehending power electronics technology. A notable aspect of this paper is its systematic approach, guiding students through a sequential progression of design, hardware implementation, and procedural steps for a series of power electronic circuits. Moreover, the paper elucidates the various tools, software, and their respective applications in the power electronics domain, contributing to a comprehensive understanding of the field.
Niraj Kumar Dewangan, Kasinath Jena, Dhananjay Kumar, K. Janardhan, B. Hemanth Kumar, and Deepak Verma
IEEE
This paper describes a Fault-Tolerant (FT) multilevel inverter (MLI) that can continue to operate even when an open switch fault (OSF) occurs in one or more power switches for PV applications. More power switches in dc-ac converters were used to achieve higher voltage quality, raising the probability of failure. This is one of the major challenges associated with the widespread use of MLI in a wide variety of industrial settings. Concurrently, the best accuracy in the output voltage can be achieved by reduced device count multilevel inverters (RDC-MLIs) at the expense of critical characteristics (such as fault-tolerant capability, charge balancing management, etc.). Reliable switching modes have been given top attention in terms of MLIs' ability to operate in fault-tolerant conditions.
Kasinath Jena, Deepak Verma, Dhananjay Kumar, Arun Rathore, Aditya Prasad Padhy, and Niraj Kumar Dewangan
IEEE
In this study, a novel active neutral point clamped switching capacitor (ANPCSC) inverter is presented, which has a voltage-boosting capacity 1.5 times that of the supply voltage. The proposed converter uses nine switches, four capacitors, and a single DC source to generate a 7-step voltage waveform at the output. To ensure the suggested topology (ST) operates properly, a Multi-carrier pulse width modulation technique based on basic logic is constructed. Overall, the voltage stress across all the switches is well within the operating range of the supply. A balancing circuit or sensor is unnecessary because floating capacitors are automatically balanced. The benefits and efficiency of the ST are demonstrated by a brief comparison with modern ANPC topologies. In order to ensure the practicality and efficiency of the ST, it has been simulated (using MATLAB/Simulink) in both steady-state and transient conditions.
Dilip Kumar Patel, Niraj Kumar Dewangan, Dhananjay Kumar, and Arun Rathore
IEEE
In this article, a new single-phase multilevel inverter is presented, one with reduced device count and less voltage stress on the power switches. Seven voltage levels are produced using this design in an asymmetrical voltage source setup. Two input dc sources and six semiconductor switches make up the proposed configuration. Complexity, cost, size, and performance were all improved by reducing power switches, DC voltage, and driving circuits. The elimination of switches, DC voltage, and driving circuits reduced complexity, size, and cost along with increased efficiency. The proposed architecture can be used for applications involving industrial drives as well as $\\mathbf{R}$ and RL loads. Comparisons are made between traditional and proposed topology based on power switch ratio, DC source, and other variables. Utilizing MATLAB/SIMULINK, the proposed asymmetrical multilevel structure is validated.
Dhananjay Kumar, Rajesh Kumar Nema, Sushma Gupta, Savita Nema, and Niraj Kumar Dewangan
Springer Science and Business Media LLC
Kasinath Jena, Chinmoy Kumar Panigrahi, Krishna Kumar Gupta, Dhananjay Kumar, and Niraj Kumar Dewangan
Springer Science and Business Media LLC
Dhananjay Kumar, Rajesh Kumar Nema, Sushma Gupta, and Niraj Kumar Dewangan
ECTI
Multilevel inverters (MLIs) are very popular in renewable energy applications and other DC to AC conversion systems due to their reliability, reduced voltage stress, low total harmonic distortion (THD), reduced filter size, low electromagnetic interference, etc. Consequently, the photovoltaic (PV) generation systems, mainly installed in remote areas, require highly reliable systems. The high failure rate of sources and power semiconductor devices results in very low reliability for inverters used in PV generation systems. The aim of this study is to develop a five-level MLI topology with fault-tolerant (FT) characteristics. Therefore, a highly resilient fault-tolerance topology, based on a cross-connected source-based MLIs (CCS-MLI) structure, is proposed in this paper. The developed CCS-MLI topology can tolerate open switch faults in any single switch failure. The proposed system and results developed in a MATLAB/Simulink environment are discussed under normal and faulty states. The simulation results are validated experimentally. Finally, the quantitative and qualitative superiority of the proposed CCS-MLI is demonstrated through the comparative analysis of other recent topologies.
Dhananjay Kumar, Rajesh K. Nema, Sushma Gupta, and Niraj K. Dewangan∗
ACTA Press
Dilip Kumar Patel, Dhananjay Kumar, Krishna Baitha, and Niraj Kumar Dewangan
IEEE
This research presents a newest boost inverter with compact switch based on a switched-capacitor approach. The primitive unit is a five-level design that creates the AC output voltage inherently due to the capacitors' self-voltage balancing. Voltage across the capacitor is maintained likely to the input voltage source using a traditional carrier-based sinusoidal modulation approach. The proposed basic unit's N-level structure is also discussed, which has added benefit of increased output voltage rise by a single input. A thorough relation with other topologies of a similar nature has been made. Several results were obtained using a laboratory prototype to assess the feasibility of the suggested main unit and its expansion for seven levels.
Nagendra Singh, Krishna Kumar Gupta, Sanjay K. Jain, Niraj Kumar Dewangan, and Pallavee Bhatnagar
Institute of Electrical and Electronics Engineers (IEEE)
Large-scale solar photovoltaic (PV) systems encounter unpredictable partial shaded conditions (PSCs). PSC, causing multiple peaks in the power–voltage (<inline-formula> <tex-math notation="LaTeX">${P}$ </tex-math></inline-formula>–<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula>) char- acteristics, potentially downgrades the performance of the PV system. However, the PV system should be operated at a global maximum power point (GMPP) for its efficient utilization. For the tracking of GMPP, a scheme based on flying squirrel search optimization (FSSO) is proposed in this work. For an effective adoption with much-reduced convergence time, the original FSSO is modified to update the squirrel position without the presence of a predator. An experimental investigation of the proposed scheme is carried out employing a quasi-Z-source converter for the extraction of maximum power under PSC. The proposed scheme yields higher tracking efficiency, nonoscillatory steady-state response, and lower transients. Simulation and experimental investigations under various shading patterns indicate that the proposed strategy outperforms other popular maximum power point tracking (MPPT) strategies based on perturb & observe (P&O), particle swarm optimization (PSO), and gray wolf optimization (GWO).
Niraj Kumar Dewangan, Tarun Kumar Tailor, Rekha Agrawal, Pallavee Bhatnagar, and Krishna Kumar Gupta
Springer Science and Business Media LLC
Modularity, efficiency, power quality, and high reliability are the attractive advantages of multilevel inverters (MLIs). But it has limitations in terms of an increased number of semiconductor devices as compared to conventional 2-level inverters. In this paper, a fault-tolerant single-phase 5-level MLI configuration is proposed. The proposed fault-tolerant configuration of the MLI can significantly improve its reliability while maintaining the modularity of its software implementation. Examination, design, and implementing thought for both normal and abnormal operating situations of the proposed MLI are presented in this paper. The feasibility of the proposed fault-tolerant MLI is verified by simulation in MATLAB/Simulink environment and experimental results in a laboratory prototype.
Jyoti Ranjan Nayak, Binod Shaw, and Neeraj Kumar Dewangan
Emerald
Purpose In this work, generation control of an isolated small hydro plant (SHP) is demonstrated by applying optimal controllers in speed governor and hydraulic turbine system. A comparative analysis of application of fuzzy PI (FPI) and PID controller is conferred for generation control (both power and terminal voltage) of an SHP. The controllers are designed optimally by using crow search algorithm (CSA) and novel hybrid differential evolution crow search algorithm (DECSA). The purpose of this paper is to settle the voltage and real power to improve the quality of the power. Design/methodology/approach In this work, the controllers (PID and FPI) are implemented in speed governor and excitation system of SHP to regulate power and terminal voltage. Differential evolution and CSA are hybridized to enhance the performance of controller to refurbish the power and terminal voltage of SHP. Findings The proposed DECSA algorithm is applied to solve ten benchmark functions, and the effectiveness of DECSA algorithm over CSA and DE is demonstrated in terms of best value, mean and standard deviation. CSA and DECSA algorithms optimized controllers (PID and FPI) are used to design SHP with the capability to contribute power and voltage of better quality. The comparative analysis to substantiate the competence of DECSA algorithm and FPI controller is demonstrated in terms of statistical measures of power and voltage of SHP. Robustness analysis is performed by varying all system parameters to prove the effectiveness of the proposed controller. Originality/value The proposed algorithm and FPI controller are applied individually to improve the quality of the power of SHP. DE, CSA and DECSA algorithms are implemented to solve benchmark equations. The solutions of all benchmark equations contributed by DECSA algorithm is converged rapidly and having minimum statistical measures as compared to DE and CSA algorithms. The DECSA algorithm and FPI controller are proposed with superior competence to enhance the generator performances by conceding undershoot, overshoot and settling time of power and terminal voltage. DECSA-based FPI controller contributes a noticeable improvement of the performances over other approaches.
Niraj Kumar Dewangan, Dhananjay Kumar, Rajesh Kumar Nema, and Krishna Kumar Gupta
IEEE
The present demand of multilevel inverter (MLI) has been increased rapidly from previous few decades, due to its reduced low harmonic components and decrease in stress across power semiconductor switches. Various topology of inverter has been proposed. This paper presents a bipolar single phase symmetrical MLI that has been incorporated to reduce device count and capable of generating five level output voltage waveform. To control the newly introduced multilevel structure a sinusoidal pulse width modulation (SPWM) scheme is used. In order to produce five level output, sources are connected in additive manner. The presented structure results in reduction of losses, number of component count, size and cost of inverter. A comparison study of the presented structure with basic conventional and some recently developed structures shows that the presented structure requires fewer numbers of device count and isolated driver circuits. The proposed design can be evaluated under different loading conditions (R-Load and RL-Load) using MATLAB/Simulink platform. The theoretical analysis and results of simulation study confirm the proper operation of the proposed inverter with experimental validation.
Pallavee Bhatnagar, Niraj Kumar Dewangan, Nagendra Singh, and Krishna Kumar Gupta
Hindawi Limited
Niraj Kumar Dewangan, Tapan Prakash, Jitendra Kumar Tandekar, and Krishna Kumar Gupta
Springer Science and Business Media LLC
High component count and subsequent effects on volume and reliability have been the major concerns for practical applications of multilevel inverters (MIs). Recent emergence of the so-called reduced component count MIs (RCC-MIs) has been driven by the attempts to reduce the number of power switches for multilevel power conversion. In many of such topologies, the aspect of fault tolerance has not been given full consideration. In this work, some of the recently proposed RCC-MI topologies have been considered and analyzed in the light of imparting fault tolerance capability in the case of open-switch failure of any one of the power switches. In an RCC-MI, the occurrence of an open-circuit fault in a power switch would often lead to shut down due to the lack of redundant switching states. To overcome these occurrences, an optimal addition of power switches is described in this work so that the desired redundant states can be synthesized. The modified RCC-MI topologies so obtained have been analyzed under the normal and faulty conditions and computer simulations have been carried out using MATLAB/Simulink, and corresponding results have been presented. The results so obtained are experimentally validated to prove the feasibility of the proposed fault-tolerant topologies.
Niraj Kumar Dewangan, Pallavee Bhatnagar, Sanjay K. Jain, Shubhrata Gupta, and Krishna Kumar Gupta
Springer Science and Business Media LLC
In this paper, some of the recently proposed reduced device count multilevel inverter (RDC-MLI) topologies are considered and analyzed in the light of imparting “any switch” open circuit fault tolerance capability. In RDC-MLIs, the occurrence of faults would shut down the system due to the lack of redundant switching states. However, for the cases involving “any single switch open circuit fault,” the system can continue to operate uninterrupted. This is achieved by adding redundant states of switching combinations, obtained by addition of switching device(s). By the proposed solution, the complete system shutdown can be prevented, thereby attaining higher reliability in RDC-MLIs. Further, the modified systems under normal and faulty conditions have been simulated using MATLAB/Simulink environment and the results are experimentally validated to prove the feasibility of the strategy for imparting fault tolerance to RDC-MLIs.
Niraj Kumar Dewangan, Krishna Kumar Gupta, and Pallavee Bhatnagar
Hindawi Limited
Pallavee Bhatnagar, Rekha Agrawal, Niraj Kumar Dewangan, Sanjay K. Jain, and Krishna Kumar Gupta
Institution of Engineering and Technology (IET)
A major disadvantage of two-stage topologies of switched capacitors based multilevel inverters is the use of H-bridge switches which endure high peak-inverse-voltage (PIV). In such topologies, the H-bridge stage is preceded by a level-generation stage which synthesises unipolar voltage levels. In this work, a bi-polar module is proposed which can synthesise nine levels at the AC terminals with a single DC input. The proposed module uses power switches with PIV equal to that of the input DC source. Use of switched capacitors in each of the proposed module enables a voltage gain of two. Such bi-polar voltage-doubler modules can be easily connected in a cascaded fashion to increase the number of levels, without involving H-bridge switches. Working modes of the module ensure that the capacitors are self-balanced. A complete analysis of the proposed module is presented. Also, experimental results are presented for validation. In addition, a comparison with other topologies has been presented.