Vemana Institute of Technology
Dr. Parameshwara M C obtained his B.E. degree from Bangalore University in Electronics and Communication Engineering in 1999, M.Tech in Electronics Engineering from BMSCE, Bangalore, Visvesvaraya Technological University (VTU) in 2007, and obtained the Ph.D. in Electrical & Electronic Engineering Sciences from VTU, Belagavi in 2018. He joined the Department of Electronics & Communication Engineering, Vemana Institute of Technology, in 2004 as a Lecturer,. Currently, he is an Associate Professor and Head of the Department . He has over 20 years of Teaching experience in Analog Electronics, VLSI, Advanced Mixed Signal design, Linear Integrated Circuits, Microelectronics, CMOS VLSI Design, Verilog HDL, and VHDL. His Area of Specialization is VLSI, Quantum Computing, and Mixed mode VLSI Design. He has published 35 research papers in National and International conferences and Journals. He is a senior member of IEEE and life member of ISTE.
BE(ECE), M.Tech(Electronics), Circuits & Systems)
Electrical and Electronic Engineering, Hardware and Architecture, Multidisciplinary, Signal Processing
Angshuman Khan, M.C. Parameshwara, and Rajeev Arya Elsevier BV
R. S. Rekha, M. C. Parameshwara, and Veerendra Dakulagi Springer Science and Business Media LLC
Rekha R. S., M. C. Parameshwara, and Veerendra Dakulagi Informa UK Limited
K. S. Shashidhara, H. Girish, M. C. Parameshwara, B. Karunakara Rai, and Veerendra Dakulagi Springer Nature Singapore
Angshuman Khan, Rupayan Das, and M C Parameshwara IOP Publishing
Abstract This study presents an ultrasound speckle suppression method to detect the stones in the human kidney. An initial image is first improved using image enhancement techniques, which are used to change the image’s intensities. Next, median filters smooth the picture and eliminate noise. Pre-processed images are segmented using a thresholding technique. The median filter extracts impulsive noise from salt-and-pepper noise. The suggested approach locates stones using location coordinates. Hospital and clinical ultrasound images were used to evaluate the proposed scheme and algorithm. The suggested scheme has been assessed by different performance measuring parameters. Physicians are likely to benefit from the research in terms of clinical diagnosis and educational training. Based on 50 test cases, the proposed plan was correct 96.82% of the time and sensitive 92.16% of the time. Furthermore, the peak signal to noise ratio is 1.82, and the average signal to noise ratio is 1.58, demonstrating the efficacy of the proposed approach.
M. C. Parameshwara and Naeem Maroof Springer Science and Business Media LLC
Angshuman Khan, M. C. Parameshwara, and Ali Newaz Bahar Walter de Gruyter GmbH
Abstract Quantum-dot Cellular Automata (QCA) is a rival to complementary-metal-oxide-semiconductor (CMOS)-based technology and one of the most cutting-edge nano-scale technologies. The multiplexer is a fundamental component in the fields of nano communication and nano computation. The investigative item of this article is the QCA multiplexer, and a handful of the best multiplexers were chosen as samples for the current experiment. The QCA layouts were designed in the QCADesigner-2.0.3 simulation engine environment, and the best one was reported after successfully experimenting on a total of eight samples. The co-ordinate-based energy was estimated using QCADesigner-E (QDE), and the non-adiabatic energy waste was investigated using QCAPro. According to the coordinates-based technique, the overall energy waste of the best energy-saving QCA multiplexer is 5.90 meV, with an average energy loss per cycle of 0.537 meV. Another approach, QCAPro-based, was used to estimate the energy loss at three different levels of tunneling at a constant temperature, yielding an overall energy loss of approximately 12 to 15 meV for the energy-efficient multiplexers..
M C Parameshwara, Naeem Maroof, and Angshuman Khan IOP Publishing
Abstract The complementary metal oxide semiconductor (CMOS) technology is approaching its physical limits due to lithographic issues and diminishing benefits of scaling. The new technologies such as quantum dot cellular automata (QCA), tunneling phase logic (TPL), nonmagnetic logic (NML), single electron tunneling (SET), etc are emerging as an alternative and may supersede the conventional CMOS technologies in the near future. Now days, the design of approximate computing based on QCA technologies has gaining much of recent interest. In this paper, a majority-logic (ML) based area-delay efficient novel approximate full adder (AFA) is presented. The QCA layout of proposed AFA is designed and simulated using QCADesigner tool. Further, the proposed AFA is analyzed and compared against the state-of-the-art approximate adders referred to as ‘reported AFAs’ (RAAs), in terms of error metrics (EMs), area, and time complexity. Also, analyzed its efficacy for error-tolerant applications such as image processing.
Angshuman Khan, Saurabh Chandra, and M C Parameshwara IOP Publishing
Abstract The design of an air quality monitoring system is a recent trend and emerging research topic using IoT and wireless sensor technology. The massive number of automobiles entering metropolitan areas contributes to increased air pollution and lower air quality, which leads to serious health problems. The paper’s primary goal is to introduce a vehicular pollution monitoring system model that can detect and measure pollutants like carbon monoxide and smoke produced by automobiles. The proposed module consists of sensors that can detect the pollutants, carbon monoxide, and smoke released by a vehicle. A Node Micro-Controller Unit (NodeMCU) will work as the brain of the sensor node and communicator with the server through wireless fidelity. The suggested system model can monitor automobile pollution, and if any vehicle exceeds a certain threshold value, it will be reported to the traffic department and the owner of the vehicle. The proposed system model is straightforward and simple, and it is predicted to be inexpensive.
M. C. Parameshwara and Angshuman Khan Springer Science and Business Media LLC
Chinna V. Gowdar and M. C. Parameshwara Springer Science and Business Media LLC
Divyansh Jangalwa, M. Nagabushanam, and M. C. Parameshwara IEEE
Multiplier is the most essential and primitive element of multiply and accumulate (MAC) unit, and is typically found in many digital signal processing (DSP) applications. Conventionally the multiplication operation is carried out through repeated addition; hence multipliers use extensively the full adders (FAs) for the addition process. The energy efficiency of the multiplier is determined in terms of power delay consumed per bit operation. Thus, FA plays a vital role in determining the overall efficiency of the multiplier. In this paper, a study, design, and simulation of an 8-bit additive multiply module (AMM) using different FA circuit architectures is presented. Further, the designed AMM is compared against the traditional Wallace and Dadda tree multipliers in terms of design metrics. To perform comparison of all the multipliers, they are described using RTL codes, simulated and verified using Cadences’ EDA tools. To extract power and area metrics, the verified designs are further synthesized under common constraints using Cadences’ generic 180 nm technology file.
M. C. Parameshwara and M. Nagabushanam Springer Science and Business Media LLC
M. C. Parameshwara World Scientific Pub Co Pte Ltd
This paper proposes six novel approximate 1-bit full adders (AFAs) for inexact computing. The six novel AFAs namely AFA1, AFA2, AFA3, AFA4, AFA5, and AFA6 are derived from state-of-the-art exact 1-bit full adder (EFA) architectures. The performance of these AFAs is compared with reported AFAs (RAAs) in terms of design metrics (DMs) and peak-signal-to-noise-ratio (PSNR). The DMs under consideration are power, delay, power-delay-product (PDP), energy-delay-product (EDP), and area. For a fair comparison, the EFAs and proposed AFAs along with RAAs are described in Verilog, simulated, and synthesized using Cadences’ RC tool, using generic 180 nm standard cell library. The unconstrained synthesis results show that: among all the proposed AFAs, the AFA1 and AFA2 are found to be energy-efficient adders with high PSNR. The AFA1 has a total [Formula: see text][Formula: see text][Formula: see text]W, [Formula: see text][Formula: see text]ps, [Formula: see text][Formula: see text]fJ, [Formula: see text][Formula: see text]Js, [Formula: see text][Formula: see text][Formula: see text]m2, and [Formula: see text][Formula: see text]dB. And the AFA2 has the total [Formula: see text][Formula: see text][Formula: see text]W, [Formula: see text][Formula: see text]ps, [Formula: see text][Formula: see text]fJ, [Formula: see text][Formula: see text]Js, [Formula: see text][Formula: see text][Formula: see text]m2, and [Formula: see text][Formula: see text]dB.
Chinna V Gowdar, M. C. Parameshwara, and Savita Sonoli IEEE
This paper proposes three novel approximate 1-bit full adders (AFA) for inexact computation. The three novel AFAs: AFA1, AFA2, and AFA3 are derived based on the conventional full adder (CFA) architecture. The performance metrics of these proposed adders are compared with state-of-the-art AFAs. For a fair comparison, the optimized Boolean expressions using ‘Karnaugh-map’ (K-map) for all AFAs under consideration are derived. Further, a dataflow description is written in Verilog and synthesized using Cadences' 180 nm standard cell library. The synthesis results show that the performance metrics of proposed adders are comparable with the state-of-the-art AFAs
Parameshwara M..C. IEEE
M. C. Parameshwara and H. C. Srinivasaiah IEEE
In this paper the spectral purity of the sine-ROM (SROM) based Digitally (or Numerically)-controlled-Frequency-Synthesizer (DCFS or NCFS) architecture is analyzed in terms of its spurious-free-dynamic-range (SFDR) metric as a function of its SROM address bus width, M (bits), its data bus width, Z (bits), "binary-frequency-control-word" (BFCW) size, and "Reference clock frequency", f<inf>clk</inf>. The M is varied from 10 to 13 bits; the Z is varied from 2 to 11 bits, which is the digitized input to the "digital-to-analog-converter" (DAC) applied with its word size W (= Z + 1) bits. Accordingly the W is varied from 3 to 12 bits, whose "most-significant-bit" (MSB) is used to offset the DAC's output to 50% of its supply voltage. The parameter BFCW has the following discrete values: 32'h00100000, 32'h01000000, 32'h01010001, and 32'h10000000 corresponding to synthesized frequency ft): ∼0.122 MHz, ∼1.95 MHz, ∼ 1.961 MHz, and ∼31.25 MHz, respectively. The highest SFDR observed in the above parameter space is 75.69 dBc corresponding to BFCW = 32'h00100000 yielding f<inf>out</inf> = 0.122 MHz for M =13 bits, and W = 12 bits. The lowest SFDR observed in this space is ∼22.35 dBc corresponding to BFCW = 32'h10000000 resulting in f<inf>out</inf> = 31.25 MHz, for M =11 bits and W = 4 bits. Further, the SFDR is also found to be a weak function of f<inf>clk</inf>, between 0.5 GHz to 3.3 GHz when observed for all the above 4 BFCWs. All these simulations are run in a technology independent Verilog-"analog-mixed-signal" (AMS) environment of Cadence's EDA tool to characterize this SROM based DCFS architecture in the above parameter space.
M. C. Parameshwara and H. C. Srinivasaiah World Scientific Pub Co Pte Lt
A novel “16 transistor” (16T) 1-bit Full adder (FA) circuit based on CMOS transmission-gate (TG) and pass transistor logics (PTL) is presented. This 1-bit FA circuit with TG and PTL structure is derived based on carry dependent sum implementation approach. The design metrics (DMs) such as power, delay, power-delay-product (PDP), and transistor-count (TC) for this 1-bit FA are compared against eight other standard and state-of-the-art 1-bit FA circuits reported till date. All the comparisons are done at post layout level with respect to the DMs under consideration. The proposed 1-bit FA dissipates an average power of 2.118[Formula: see text][Formula: see text]W, with a delay of 606 ps, with an area of 33.1[Formula: see text][Formula: see text]m2, resulting in a PDP of 1.28 fJ. This power and hence the PDP is the lowest of all, ever reported till date. In this comparative study a common test bench with a supply voltage [Formula: see text][Formula: see text]V, input signal frequency [Formula: see text][Formula: see text]MHz is used. This 1-bit FA is designed and implemented using Cadences' 90[Formula: see text]nm “generic-process-design-kit” (GPDK).
M. C. Parameshwara and H. C. Srinivasaiah IEEE
In this paper we propose a novel approach to compress the size of sine Read Only Memory (sROM) using a Sine Linear-Phase-Offset Difference (SLPOD) method. The sROM is a sine look-up table memory and is used to store sine approximation errors corresponding to an angle [0, π/2). The sine approximation errors can be computed by using the state-of-the-art sROM compression techniques. The Sine Linear-Phase Difference (SLPD) method is one such compression technique that saves two bits in the sROM output word. The SLPOD method is a novel compression technique derived based on the traditional SLPD technique. In a proposed method the sROM stores the values of sine approximation error that are derived using the SLPOD approach. This approach of deriving sine approximation error greatly minimizes the maximum value of difference that occurs between the quadrant sine function and the linear-phase. To obtain sine approximation error using SLPOD approach we divide the linear-phase `x' (where x ε [0, 1)) into `k' segments (where k is chosen as positive integer powers-of-2) and each segment is offset by a constant value (ε [0, 1)). Using this proposed SLPOD approach we can save N = log2(k) bits in sROM output word.