Dr.Latha Rajagopalan
@hkbk.edu.in
Professor & Head
HKBK College of Engineering
Dr. R. Latha (Rajagopalan Latha) obtained her Bachelor’s degree in Electronics and Communication Engineering and Master’s degree in Applied Electronics from Bharathiar University , TamilNadu, India, She pursued her Doctorate in the area of Multi rate DSP and Low Power VLSI Design from Anna University-Chennai, TamilNadu, India. She has rich academic & research experience of about 24.9 years. Her specializations include Microelectronics, Microcontroller Architecture Design, Digital Signal Processing and VLSI Design. Her current research interests are in the area of Multi-rate Digital filter design, Wireless Communication and Architecture Optimization using HDL’s. She is a Member of IEEE, IETE, ISTE, IAENG, SEEE, NFED and SSI. She has completed four AICTE sponsored/research projects as a Principal Investigator. She has about 107 technical and research publications and presentations to her credit in International Journals and Conferences.
EDUCATION
B.E -Electronics & Communication Engineering
M.E- Applied Electronics
Anna University
RESEARCH INTERESTS
Low Power VLSI and Multirate DSP
Scopus Publications
Scholar Citations
Scholar h-index
Scholar i10-index
Scopus Publications
K. Hemavathi and R. Latha
IEEE
Networks have an important role to play in modern life, and cyber security is an active research area. An Intrusion Detection System (IDS) becomes a crucial cyber security method that monitored the state of hardware and software running in the network. IDS can find attacks in available environments. The Machine Learning (ML) method is one among the emerging approaches that have better performance in the situation they have encountered already, and enjoy a wide variety of applications in outlier analysis speech recognition, pattern detection, and so on. With unbalanced data, the predictive model established utilizing ML method might produce an unacceptable classifier that affects the accuracy of predicting intrusion. Conventionally, researcher workers applied oversampling and undersampling to balance data in the dataset for overcoming these problems. Therefore, this article presents a Deep Learning with Conditional Generative Adversarial Network-based Intrusion Detection System (DLCGAN-IDS) technique on Balanced Data. The goal of the DLCGAN-IDS technique lies in the proper balancing of the network samples and identify the intrusions accurately. To accomplish this, the presented DLCGAN-IDS approach primarily normalizes the input data by employing min-max normalization. For imbalanced data handling, the CGAN approach is used for balancing the sample numbers in the dataset. Finally, DL based Long Short-Term Memory (LS TM) method is enforced for detecting and classifying intrusions in the network. The results of the DLCGAN-IDS method execute on the IDS dataset. The comprehensive outcomes pointed out the superior achievement of the DLCGAN-IDS model over other current algorithms.
S. Vimalkumar and R. Latha
IEEE
Maize is a main global food crop and is the most productive grain crop. It is also an optimum feed for the progress of animal husbandry and crucial raw material for the chemical industry, light industry, health medicine, and. Diseases are the significant factor limiting the high and stable yield of maize. For classifying diseases based on that damages the plants, the leaves of affected plants can be studied utilizing pixel-wise approaches. The Convolutional Neural Network (CNN) is the most effectual Deep Learning (DL) algorithm utilized in classification of an image to correctly diagnose plant ailments. Therefore, this study introduces an automated Maize Leaf Disease Detection using Biogeography-based Optimization with Deep Learning (MLDDBBODL) algorithm. The presented MLDD-BBODL method aims to identify and classify the occurrence of maize disease accurately. To achieve this, the presented MLDD-BBODL method employs contrast enhancement as an initial preprocessing stage. Besides, the SqueezeNet model is exploited for the derivation of feature vectors. Meanwhile, a Backpropagation Neural Network (BPNN) classifier is utilized for the recognition of maize leaf ailments. Furthermore, the BBO technique is implemented for the parameter tuning of the BPNN model which in turn enhances the classification results. The performance evaluation of the MLDD-BBODL technique is carried out on the leaf disease dataset. An extensive comparison study stated that the MLDD-BBODL technique reaches outperformed results over other recent approaches in terms of different measures.
Latha R, Suhas A R, B P Pradeep Kumar, M.Mohammed Ibrahim, and Sathiyapriya V
IEEE
Speech Enhancement (SE) aims to improve the quality of degraded speech while maintaining its intelligibility. The Wavelet Transform (WT) has become a powerful tool of signal analysis thereby widely used in signal detection and signal denoising. In this paper, we propose an effective means of SE by a hybrid threshold scheme using WT. The proposed methodology looks into both falling the noise and preserving edges of the speech signal unlike the conventional Hybrid Threshold (HT) and Soft Threshold (ST) in the wavelet domain. The threshold value in the wavelet domain is maintained constant for all sub-bands of the signal which reduces denoising efficiency. A novel speech augmentation technique built on the wavelet onsets and time adaption of introduced by calculating wavelet coefficients of the Teager Energy. Performance analysis of speech enhancement techniques using Wavelet coefficients and Teager Energy Operator (TEO) with hybrid threshold method is done. The experiment is carried out for speech data with various values of SNR vacillating from -10 to +10 db with Additive White Gaussian Noise (AWGN).
S. Thirumal and R. Latha
IEEE
Crop yield prediction is a not a simple task in precision agriculture. To be specific, paddy is one of the globally significant cereal crops and extremely important for decision-making and crop management. Although there exist more crop yield prediction methods, but lacks a better outcome in paddy yield prediction. Attaining optimal crop yield was always a difficult task for the farmer because of changeable ecological conditions. The main factor for uncertainty of crop yield are changing nature of weather, land types, and availability of resources. Hence, the scientists around the world making continuous efforts to find methods, which can precisely and efficiently predict the crop, yield in much advance such that the agronomists can make best course of action to encounter the future challenges. Rice yield prediction includes estimation of the amount of rice that would be produced in a specific area, generally a region or a farm, related to several factors that could affect the crop yield. Therefore, this article introduces an Automated Rice Crop Yield Prediction using Sine Cosine Algorithm with Weighted Regularized Extreme Learning Machine (SCA-WRELM). The proposed SCA-WRELM technique aims to forecast the rice crop productivity effectually. To do this, the SCA-WRELM technique performs min-max data normalization process to scale the data into uniform format. For yield prediction, the SCA-WRELM technique uses WRELM model to forecast the rice productivity. Finally, the SCA is exploited for the optimal parameter tuning of the WRELM model and it results in improved predictive results. The simulation values of the SCA-WRELM approach is tested on rice yield dataset and the outcomes demonstrate the improved outcomes of the SCA-WRELM approach over other existing methods.
Mahesh Aganti, Kowsik. B, Latha R, and C. Bharatiraja
IEEE
Resonant Inductive Power Transmission (RIPT), a wireless power transfer technology, is a cutting-edge option for Electric Vehicle (EV) battery charging systems. RIPT is a safe and practical method of charging electric cars (EVs). RIPT systems must have high-power transmission, dependability, robustness, and cost in order to achieve highway charging. This study illustrates a multi-legged dynamic wireless charging system wherein each leg of the inverter is utilized separately for every transmitter coil to bring down the system cost. Each space between two transmitters coils a sensor attached to the road pavement that serves as a trigger when a receiver coil passes over a path used for charging. This work's transmitter part includes a proposal for a multi-leg converter. To drive a transmitter coil, each leg of the converter acts as a half-bridge high frequency inverter circuit. The proposed system achieved 76% in experimental analysis.
R. Latha, C. Venkatesan, A.R. Suhas, and T. Thamaraimanalan
IEEE
The main focus of this work is to propose suitable architectures for the decimation filter networks of digital receivers that use the reduced logic and are capable of receiving multiple communication standard signals. It also involves the design, simulation, and implementation of multi-stage multi-rate filter architectures with reduced Very Large Scale Integrated (VLSI) cost functions. In the first multi-stage architecture namely, the Multi-Standard Decimation Filter (MSDF) structure is proposed to cater to the need of reception of multi-standard receiver signals. The MSDF architecture is designed for GSM and WiMAX wireless communication specifications and its first stages are designed using Cascaded Integrator Comb (CIC) filters. In the second architecture, a modified MSDF structure is implemented using polynomial CIC filters to meet the multi-standard requirements. The third architecture concentrates on design parameters of polyphase CIC-based decimation filter and its implementation concepts. Spartan FPGA-based implementation results that the proposed polynomial CIC-based MSDF architecture provides 32.11% of area reduction when related with the multistage MSDF. The proposed polyphase CIC-based MSDF architecture provides 28.57% of dynamic power-saving and a 15.5% increase in speed when compared to polynomial-based MSDFC architecture. Thus, the proposed polyphase MSDF architecture provides low power and lesser delay solutions using a multistage decimation approach and it is best suited for multi-standard communication applications in digital receivers.
R. Punithavathi, R. Thanga Selvi, R. Latha, G. Kadiravan, V. Srikanth, and Neeraj Kumar Shukla
Computers, Materials and Continua (Tech Science Press)
G. Madasamy Raja, Mohamed Thaha, R. Latha, and A. Karthikeyan
Springer Science and Business Media LLC
The main focus of this paper is to improve the performance of the texture model Optimized Local Ternary Patterns (OLTP), which is known as one of the successful variants of the texture model Local Binary Patterns (LBP), a well known method for texture analysis and its applications. Generally preprocessing is used in digital image processing for reducing the unwanted noise and disturbances in such a way that it improves the quality of the image. Preprocessing not only removes the distortions but also enhances the features of the image for further processing. To achieve better recognition accuracy, the texture model OLTP was combined with a preprocessing method that uses nonlinear diffusion method as a preprocessing tool in this paper, with the hope that this idea will surely improve the local feature description and texture classification process. This nonlinear diffusion method uses two newly developed edge stopping functions for preprocessing. This proposed method is tested with two standard texture datasets namely Brodatz Dataset and Usptex dataset. The results show that the use of the preprocessing step really improved the texture classification accuracy.
R. Latha and R. Nadarajan
Elsevier BV
Today, Digital world plays a vital role in new era of science and technology. The main objective of the proposed research work is to provide information about the particular location based on similes and not as a document. So that the customer or the user can predict information about the particular place from the existing customer. This Information of the particular place is categories based on the necessity of the user. This proposed work provides web service, where the user has to enable the geo location of the mobile device, based on the geolocation questionnaire will be asked to the customer randomly. These Emotional Intelligence service will provide information to the new user; based on the ranking provided by the existing user, based on affective and factual knowledge
Latha Rajagopal
Springer Science and Business Media LLC
This paper reports on the synthesis and implementation of a digital decimation filter suitable for multi-standard transceivers. Decimation filter architectures used in transceivers must be capable of providing low power and less area. In this paper, three different architecture designs namely Decimation Filter with Conventional MAC Unit, Cascaded Multi-Standard decimation Chain and Hybrid structure are proposed to meet the demand of low power and area efficient digital decimation filter. The filter architectures are implemented using FPGA and its performances are tested. The architectures are tested using conventional number system and with two different encoding schemes of filter coefficients called canonic signed digit and minimum signed digit. The implementation results reflect that considerable reduction in area of 47.9 % and power reduction of 28.6 % are achieved using hybrid architecture, when compared with conventional MAC and cascaded chain architectures.
C. Bharatiraja, S. Jeevananthan, J.L. Munda, and R. Latha
Elsevier BV
C. Bharatiraja, Seenithangam Jeevananthan, Ramachandran Latha, and V. Mohan
Institution of Engineering and Technology (IET)
The purpose of this study is to provide a broad idea about current control scheme and equilibrating voltages in DC-link capacitors of the neutral-point clamped multilevel inverter (NPC-MLI), using an innovative hexagonal space vector hysteresis current control (SVHCC) scheme. The main ideology is to force the literal current vector to reach the reference current vector through an appropriate voltage vector selection sequence. This proposed scheme defines two hexagonal hysteresis bands encompassing the error vector, as a first step. With respect to the error vector location, the selection of the adjacent vector is acted to minimise the error vector. In addition to the error vector selection, the capacitor voltage is also equilibrated by controlling the degree of freedom available in selecting the switching vectors. The SVHCC scheme is intelligent in performing modulation depth dependent selection of switching vectors between the groups namely closest three vector and preferred three vector (PTV). This scheme balances the DC-link capacitors’ voltages within a tolerance limit for any value of modulation index. The proposed scheme is asserted through MATLAB/Simulink software. The superiority of the proposed technique is validated through the 2 kW NPC-MLI supported with SPARTAN III 3AN –XC3S400 field programmable gate array.
R Latha, , P T Vanathi, and
School of Electrical Engineering and Informatics (STEI) ITB
This paper addresses on three different architectures of digital decimation filter design of a multi-standard RF transceivers. Instead of using single stage decimation filter network, the filters are implemented in multiple stages using FPGA to optimize the area, delay and dynamic power consumption. The proposed decimation filter architectures reflect the considerable reduction in area and dynamic power consumption without degradation of performance. The filter coefficients are derived from MATLAB, the filter architectures are implemented and tested using Xilinx SPARTAN FPGA .First, the types of decimation filter architectures are tested and implemented using conventional binary number system. Then the two different encoding schemesi.e. Canonic Signed Digit (CSD) and Minimum Signed Digit (MSD) are used for filter coefficients and then the architecture performances are tested .The results of CSD and MSD based architectures show a considerable reduction in the area and power against the conventional number system based filter design implementation. The implementation results reflect that considerable reduction in area of 47.89% and dynamic power reduction of 28.64% are achieved using hybrid architecture.
C. Bharatiraja, S. Jeevananthan, and R. Latha
Elsevier BV
C. Bharatiraja, R. Palanisamy, Sushuruth Sadagopan, R. Latha, and S.S. Dash
Trans Tech Publications, Ltd.
A Split inductor is used with Exiting Inverter to interconnect inverter with grid connected system which avoids the usage of transformer. While using split inductor NPC-MLI shoot-through problems are producing in the bridge legs of an NPCTLI, its operation stability is ruined. Hysteresis Current Control (HCC) offers an excellent current control performance to NPCTLI. It acts based on the error current value i) and hysteresis band value (h). The proposed topology guarantees for no common-mode voltage, shoot-through possibility and capacitor balancing problem. Finally, the simulation results of a proposed SI-NPCTLI system verified using MATLAB SIMULINK.
C. Bharatirajal, S. Raghu, S. Jeevananthan, and R. Latha
IET
This paper proposes a novel torque control scheme for induction motors. Compared with field orient control (FOC), direct torque control (DTC) is known to provide fast and robust response for induction motors. However, while offering high dynamic performance, classical DTC produces notable torque, flux, and current ripples, and operates with a variable inverter switching frequency. The proposed direct torque scheme is combined with simplified Space Vector Pulse Width Modulation (SVPWM) technique to control the inverter output voltage. The desired voltage vector for the inverter for controlling the torque is given by the proposed DTC SVM scheme. The direct torque control is based on the relation ship between instantaneous slip angular frequency and rotor angular frequency in adjustment of the reference stator flux angle. The amplitude of the reference stator flux is always kept constant at rated value. The proposed scheme therefore provides smooth, fast and robust regulations of the electrical torque and the stator flux. Simulation results are provided to evaluate the performance of the proposed scheme. The proposed scheme has been implemented in FPGA. Experimental results have been provided to evaluate the motor performance.
RECENT SCHOLAR PUBLICATIONS
MOST CITED SCHOLAR PUBLICATIONS
Publications
1. Power and Area Efficient Decimation Filter Architectures of Wireless Receivers in Springer Journal “Proceedings of the National Academy of Sciences, India Section A: Physical Sciences”, Volume 87, Number 1, March 2017 ISSN: 0369-8203, PP: 83-96.
2. Texture classification using optimized local ternary patterns with nonlinear diffusion as pre-processing” in Springer Journal “Multimedia Tools and Applications” Volume 67, Issue 1, January 2019, ISSN: 1380-7501 (Print) 1573-7721 (Online),,PP: 3831-3846.
GRANT DETAILS
1. AICTE Sponsored PMKVY(TI): 2 (Worth Lakhs)
2. R&D Projects: 2 (Worth Lakhs)
RESEARCH OUTPUTS (PATENTS, SOFTWARE, PUBLICATIONS, PRODUCTS)
1. Electronic Lock System with Multi-level Access. Application No:201841046549
2. Electronic Device & Security question & Answer based Multi-locking Method Thereof. Application No:201941011598
3. Electronic Device & Colour based Multi-locking Method Thereof.
Application No:201941009477
4. Electronic Device & Speed based Multi-locking Method Thereof.
Application No:201941009476
5. Electronic Device & Kolam based Multi-locking Method Thereof.
Application No:201941011603
6. Electronic Device & Multi-type Forgot Password Recovery & Reset Methods Thereof. Application No:201941011601
7. Wireless Fidelity with Dynamic Authentication Method. Application No: 202041039079
CONSULTANCY
Posted as a trainer at M/s Robert Bosch Engineering and Business Solutions Ltd., Coimbatore for trainees & handled sessions on “Software Development Life Cycle in Embedded Systems” on 13.08.2011-30.09.2012.