Design and Analysis of Low Power MAC for DSP Processor Ravi Shankar Mishra, Puran Gour, Sandeep Dhariwal, Gaurav Kumar, Anubhav Anand 2023 International Conference on Artificial Intelligence and Applications Icaia 2023 and Alliance Technology Conference Atcon 1 2023 Proceeding, 2023 This research article represents low-power MAC architecture, which is one of the main building blocks of DSP processors. The MAC unit consists of three important blocks: a multiplier for multiplication, an adder for addition, and an accumulator for storing the results. So, by reducing the power dissipation of multiplier and adder units, we can propose a low-power MAC architecture. In this paper, first a low-power Baugh-Wooley multiplier (with a proposed 2S-T full adder design) and a conventional Baugh-Wooley multiplier (with an existing 2S-T full adder design) are analyzed using Cadence Virtuoso. The proposed full-adder-based Baugh-Wooley multiplier exhibits 32.41 microwatts of power dissipation, which is much less than the conventional Baugh-Wooley multiplier’s power consumption of 2.743 milliwatts. After multipliers, a MAC unit with a conventional multiplier is also simulated with 2.743 milliwatts and using the proposed multiplier with a significant power reduction of 0.5504 milliwatts.
Design and simulation of low power voltage controlled oscillator for biomedical applications Deepak Sajotra, Sandeep Dhariwal, Ravi Shankar Mishra, Raghav Gupta, Vijay Kumar Lamba Proceedings 2nd International Conference on Intelligent Circuits and Systems Icics 2018, 2018 In current scenario the need of low power VLSI applications is of high importance for biomedical applications. Voltage Controlled Oscillator is one of the CMOS devices which is used in Phase Locked Loop circuits, clock circuits, frequency generation circuits etc. For biomedical applications (Pacemaker) frequency should be low in corresponding to the heartbeat. This paper presents a novel approach on frequency modulation in Voltage Controlled Oscillators. The design of Current Starved VCO is taken into consideration and various analysis is done in accordance to modulate the output oscillating frequency of a VCO. The normal frequency of oscillations of a VCO from 7.2 GHz is reduced to 1.3 Hz and less. Various analysis like Transient response, Frequency Response, Power and Parametric analysis has been observed through simulation results in 45nm CMOS Technology using Cadence Virtuoso Tool. Output frequency is analyzed with respect to varying input voltage in range of 0.5V to 1V using parametric analysis. An approach to use VCO as a low power, low frequency device for various applications is explored.
METAPUF a challenge response pair generator Abhishek Kumar, Suman Lata Tripathi, Ravi Shankar Mishra Periodicals of Engineering and Natural Sciences, 2018 Physically unclonable function (PUF) is a hardware security module preferred for hardware feature based random number and secret key generation. Security of a cryptographic system relies on the quality of the challenge-response pair, it is necessary that the key generation mechanism must unpredictable and its response should constant under different operating condition. Metastable state in CMOS latch is undesirable since it response becomes unpredictable, this feature used in this work to generate a unique response. A feedback mechanism is developed which forces the latch into the metastable region; after metastable state, latch settle to high or state depends on circuit internal condition and noise which cannot be predicted. Obtained inter hamming variation for 8 PUF is 51% and average intra hamming distance is 99.76% with supply voltage variation and 96.22% with temperature variation.
Design of a high performance 4 bit multiplier using UT algorithm with domino logic N. Lokabharath Reddy, Mohinder Bassi, Ravi Shankar Mishra 7th IEEE Annual Information Technology Electronics and Mobile Communication Conference IEEE Iemcon 2016, 2016 4×4 Vedic multiplier using domino logic is proposed in this paper. The designs are implemented in GPDK 90nm technology on cadence virtuoso tool using spectre simulator. Multiplication is a fundamental operation, which is widely used in many digital signal processing systems, multimedia applications, computers and many digital systems. Power and delay are two important design constraints but there is always a trade-off between them, so power delay product (PDP) is the better constrain to evaluate the circuit performance. The performance of the multiplier is improved by improving the performance of basic blocks of multipliers .i.e. full adders and half adders. Here the extra signal is required to control the inputs .i.e. clock signal. Due to the introduction of clock signal in circuit, the complexity of the circuit is increases. Although it uses a clock signal, the total average power consumption of 4×4 multiplier is very less compared to any other circuit in the present. From the simulation results, the average power consumption of 4×4 multiplier is in 19.5 μw and delay is in 1.67ns. The proposed design having the good performance all over the circuit at present.
Challenge-response generation using RO-PUF with reduced hardware Abhishek Kumar, Ravi Shankar Mishra, K R Kashwan 2016 International Conference on Advances in Computing Communications and Informatics Icacci 2016, 2016 Cryptography looks forward to generate secrete key from integrated circuit. A silicon based device having uncontrollable feature in term of measurable output can turned into physically unclonable function (PUF). Multiplexer based PUF works on unpredictable delay difference between two parallel paths, while Ring oscillator based PUF works on frequency deviation generated due to random variation of CMOS fabrication process. Hardware based intrinsic features must include to generate a random response which fuzzified to generate a reliable secret key. Our design incorporates PUF based on circuit variation instead of process variation, PISO shift register reduce the hardware compared to existing RO-OUF. A 4-bit challenge generates 16-bit random response with measured reliability in term of intra hamming distance approx to mid value.
Comparative analysis of different algorithm for design of high-speed Multiplier Accumulator unit (MAC) P. A. Irfan Khan, Ravi Shankar Mishra Indian Journal of Science and Technology, 2016 Background/Objectives: Power consumption is one of the important designsin many digital signal processing applications, the main building blocks of the processor is Multiplier-Accumulator (MAC) unit. Methods/Statistical Analysis: In the present work, the Baugh-Wooley multiplier is implemented for improving the performance of MAC unit. The Baugh wooley multiplier is faster than the other multipliers like Array multiplier, Wallace tree multiplier, Booth multiplier. The MAC unit using Baugh-Wooley multiplier is implemented using 180nm technology in cadence virtuoso. Findings: The speed of MAC unit using Wallace tree multiplier is 93.6MHz and with Baugh wooley multiplier is 99.1MHz. The power consumption of the MAC unit using Wallace tree multiplier is 2.265mW and with Baugh wooley multiplier is 4.628mW. The results show that the MAC unit using Baugh wooley multiplier is faster than the Wallace tree multiplier. Application/Improvements: MAC unit processors. In future, we can implement MAC unit using Baugh wooley multiplier with apipelining technique such that the total power consumption will be less.
PUF based challenge response pair for secured authentication International Journal of Control Theory and Applications, 2016
Comparative analysis of 4-bit and 8-bit galois encoder in 90 nm technology International Journal of Control Theory and Applications, 2016
