Aadil Anam

Scopus Publications

Electro-thermal and switching performance of a heteroepitaxial π-Gate β-Ga₂O₃ MOSFET on a 4H-SiC substrate
Md Zafar Alam, Imran Ahmed Khan, S. Intekhab Amin, Aadil Anam
Micro and Nanostructures, 2026
Heteroepitaxial β-Ga2O3 Trench-Gate MOSFET on 4H-SiC: Trap, Thermal, and Breakdown Optimization
Md Zafar Alam, Imran Ahmed Khan, Syed Intekhab Amin, Aadil Anam
Physica Status Solidi A Applications and Materials Science, 2026
A heteroepitaxial β‐Ga 2 O 3 trench‐gate MOSFET on a 4H‐SiC substrate incorporating a variable lateral doping (VLD) profile is proposed and analyzed using physics‐based technology computer‐aided design (TCAD) simulations. The trench architecture improves gate electrostatics, while the VLD drift engineering reduces electric‐field crowding and enhances breakdown robustness. The optimized device achieves a drain current of 341 mA/mm, a specific on‐resistance of 8.5 mΩ cm 2 , and an off‐state breakdown voltage of 2838 V, yielding a high‐power figure of merit of 491 MW/cm 2 . Deep‐level trap modeling is included to assess the influence of oxide and heterointerface states on device characteristics. Temperature‐dependent simulations (300–500 K) further evaluate the combined effects of traps, band‐tail states, and phonon scattering on key electrical parameters. Electro‐thermal analysis confirms that the 4H‐SiC substrate significantly mitigates self‐heating, maintaining substantially lower peak lattice temperatures than native β‐Ga 2 O 3 across a wide range of operating conditions. These results highlight the combined advantages of trench‐gate design, VLD drift optimization, and SiC‐based thermal management, establishing the proposed β‐Ga 2 O 3 /4H‐SiC MOSFET as a promising candidate for high‐voltage, high‐efficiency power switching applications.
β-Ga2O3 trench-gate MOSFET with VLD and field plate design for enhanced RF, thermal, breakdown voltage, and switching application
Md Zafar Alam, Imran Ahmed Khan, Syed Intekhab Amin, Aadil Anam
Physica Scripta, 2026
This study proposes a high-performance β -Ga 2 O 3 trench-gate (TG) MOSFET employing a variable lateral doping (VLD) scheme to strengthen power-device capability. The analysis examines the impact of VLD engineering, high-κ HfO 2 and Al 2 O 3 dielectrics, and field-plate structures on the electrical, thermal, and radio-frequency (RF) characteristics. HfO 2 demonstrates lower ON-resistance and higher transconductance than Al 2 O 3 , along with reduced temperature sensitivity. The β -Ga 2 O 3 TG-MOSFET achieves picosecond-scale switching, with a turn-on delay of 31.6 ps and rise time of 33.2 ps, supported by low parasitic capacitances (C iss = 126.1 fF mm −1 , C rss = 89.5 fF mm −1 ). The turn-off transition (t d(off) = 1.2 ns, t f = 7.7 ns) confirms suitability for high-frequency power and RF operation. Incorporating dual field plates raises the off-state breakdown voltage from 2058 V to 3045 V an increase of 48% by lowering peak electric fields and redistributing the lateral field profile. The results confirm that the synergy between trench-gate design, lateral doping engineering, and dielectric optimization in β -Ga 2 O 3 markedly enhances switching behavior, heat management, and breakdown strength, making the proposed architecture a compelling solution for advanced high-power, high-temperature, and RF applications.
Design and Analysis of Mg2Si Source Based Vertical Quantum Tunneling Transistor to Enhance DC Switching Performance and its Application as Biosensors
Maryam Raza, Imran Ahmed Khan, M. Nizamuddin, Aadil Anam
Silicon, 2026
Cryogenic and Quantum Simulation of Short Channel 30 nm SOI MOSFET: An NEGF Quantum Simulation
Aadil Anam, S. Intekhab Amin, Dinesh Prasad
Silicon, 2025
Science and technology of tunnel field-effect transistors
Zuber Rasool, Nuzhat Yousf, Aadil Anam, S. Intekhab Amin
Field Effect Transistors, 2025
Currently, the most used transistor technology is none other than metal-oxide-semiconductor field-effect transistor (MOSFET). It has been working well according to the Moore's law for nearly six decades. As the demand of miniaturization of electronic gadgets is increasing rapidly, the major concern is, will MOSFETs be able to cope with the growing demand? The answer is, No! MOSFET technology has served well, but now it needs a farewell, like every other technology used in present will become past in future. The increase in short-channel effects and subthreshold limit (Boltzmann's Tyranny) are two of the major reasons not favoring the use of this technology in near future. Tunnel field-effect transistor (TFET) has advantage of higher ON to OFF current ratio as well as steep subthreshold slope and faster switching characteristic owing to band-to-band tunneling mechanism. The focus of this chapter is on the same. The chapter starts with discussing the quantum physics approach of tunneling then short comings of MOSFET technology and finally move toward the TFET technology. Physics and working mechanism of the TFET in ON state, OFF state, and ambipolar state is explained in detailed manner. The factors influencing the performance of TFETs are discussed as well. Types of tunneling mechanism, i.e., line tunneling and point tunneling are discussed. Approaches to increase ON-state performance and reduce ambipolarity like pocket doping, Ge source, underlapping, and doping-less TFET are simulated with technology computer-aided design (TCAD) and direct current (DC) and radio frequency (RF) performance of all these configurations are discussed in detail manner. A brief comparison of some already available TFET devices and their DC and RF performance parameter's comparison is done. At last, applications of TFET devices in various fields like sensing and neuromorphic computing have been discussed.
Design and Analysis of High-Performance Schottky Barrier β-Ga2O3 MOSFET With Enhanced Drain Current, Breakdown Voltage, and PFOM
Md Zafar Alam, Imran Ahmed Khan, S. Intekhab Amin, Aadil Anam, Mirza Tariq Beg
International Journal of Numerical Modelling Electronic Networks Devices and Fields, 2025
In this article, a Schottky barrier β‐Ga2O3 MOSFET is proposed. It shows improvements in drain saturation current, Ion/Ioff ratio, transconductance, and off‐state breakdown voltage. The proposed design, which implements the Schottky barrier source and drain contacts, has led to reduced on‐state resistance (Ron), reduced forward voltage drops, faster switching speed, higher frequency, and improved efficiency. After device optimization, we determined that a source and drain having a work function of 3.90 eV result in the highest drain saturation current of (Ids) 264 mA. Additionally, in the transfer characteristics, we demonstrate that increasing the channel doping concentration led to a shift toward depletion mode operation, while decreasing the doping concentration moved the device toward enhancement mode at the cost of drain current. Analysis of lattice temperature and self‐heating effects on different substrates has also been performed. Furthermore, introducing a passivation layer of SiO2 as a gate oxide and an unintentionally doped (UID) layer of 400 nm doping concentration of 1.5 × 1015 cm−3, results in further significant improvements in the drain saturation current (Ids) of 624 mA and transconductance of 38.09 mS, approximately doubling their values compared with the device without a passivation layer of SiO2 and an Ion/Ioff ratio of 1015, and the device's performance at various substrate temperatures has been evaluated. In addition, the inclusion of a passivation layer of SiO2 improves the breakdown voltage to 2385 V, which is significantly high compared with the conventional device. Moreover, the lower specific‐on‐resistance Ron,sp of 7.6 mΩ/cm2 and higher breakdown voltage then the high‐power figure of merit (PFOM) (BV2/Ron,sp) of 748 MW/cm2 have been achieved.
III-V material-based junction-free L-shaped gate normal line tunneling FET for improved performance
Aadil Anam, S Intekhab Amin, Dinesh Prasad
Semiconductor Science and Technology, 2024
In this paper, we introduce a novel III–V compound material-based junction-free (JF) L-shaped gate normal line tunneling field-effect transistor (III–V JF L GNLTFET) for improved output performance at 0.5 V operation. The key design metric, i.e. JF or junctionless design, in our device eliminates issues like random dopant fluctuations (RDF) and high thermal budgets and streamlines the fabrication. The implementation of III–V compound material, i.e. low bandgap compound GaSb, in the source region, combined with the larger area gate normal line tunneling, improves the ON current for our proposed III–V JF L GNLTFET device. Additionally, the utilization of large bandgap GaAs compounds on the drain and channel sides eliminates ambipolarity and further enhances the performance of our proposed device. Meaning that the proposed device simultaneously improves the ON current and suppresses the ambipolarity. Our proposed III–V JF L GNLTFET exhibits enhanced output performance with an ON current of 23.2 μA μm−1 and a minimum and average subthreshold swing of 3.7 mV dec−1 and 15.82 mV dec−1 respectively. Furthermore, the proposed III–V JF L GNLTFET also gives superior RF/analog performance with transconductance (168.65 μS), cut-off frequency (33.52 GHz), gain-bandwidth product (5.11 GHz), and transconductance-frequency product (243.7 GHz).
Novel III-V inverted T-channel TFET with dual-gate impact on line tunneling, with and without negative capacitance
Aadil Anam, S. Intekhab Amin, Dinesh Prasad
Microelectronics Journal, 2024
Raised Ge-Source with n+ pocket and recessed drain line TFET: A proposal for biosensing applications
Aadil Anam, S. Intekhab Amin, Dinesh Prasad
Materials Science and Engineering B, 2024
Ultralow-Power DST-TFET pH Sensor Exceeding the Nernst Limit with Influence of Temperature on Sensitivity
Nuzhat Yousf, Aadil Anam, Zuber Rasool, S. Intekhab Amin
ACS Applied Bio Materials, 2024
Exploring Intertwined quantum and cryogenic behaviour in ultra-scaled 10 nm MOSFET: a NEGF quantum ballistic simulation
Aadil Anam, S Intekhab Amin, Dinesh Prasad
Physica Scripta, 2024
Effect of ambipolarity suppression in PNPN TFET with dopant segregated Schottky-drain technique
Aadil Anam, S. Intekhab Amin, Dinesh Prasad, Naveen Kumar, Sunny Anand
Microelectronics Journal, 2024
Performance Analysis of InSb Source-Based Heterojunctionless Nanowire TFET for Low-Power Application: Design and Simulation
Aadil Anam, S. Intekhab Amin, Dinesh Prasad
2024 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation Iatmsi 2024, 2024
Optimizing InGaAs/GaAsSb Staggered Bandgap U-Gate Line TFET With p+-Pocket Implant and Negative Capacitance for Enhanced Performance
Aadil Anam, S. Intekhab Amin, Dinesh Prasad
IEEE Transactions on Nanotechnology, 2024
InSb Source-Based Heterojunctionless Nanowire Tunneling FET for Biosensing Application: Design and Analysis
Aadil Anam, S. Intekhab Amin, Dinesh Prasad
2024 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation Iatmsi 2024, 2024
Charge-plasma-based inverted T-shaped source-metal dual-line tunneling FET with improved performance at 0.5 V operation
Aadil Anam, S Intekhab Amin, Dinesh Prasad, Naveen Kumar, Sunny Anand
Physica Scripta, 2023
Analysis of III-V material-based dual source T-channel junction-less TFET with metal implant for improved DC and RF performance
Aadil Anam, S. Intekhab Amin, Dinesh Prasad, Naveen Kumar, Sunny Anand
Micro and Nanostructures, 2023
Undoped vertical dual-bilayer TFET with a super-steep sub-threshold swing: proposal and performance comparative analysis
Aadil Anam, S Intekhab Amin, Dinesh Prasad, Naveen Kumar, Sunny Anand
Semiconductor Science and Technology, 2023
Temperature Sensitivity and Reliability Study of Symmetrical U-Shaped Gate Line TFET: RF/Analog and Linearity Performance Analysis
Aadil Anam, S. Intekhab Amin, Dinesh Prasad
Proceedings 2023 IEEE International Symposium on Smart Electronic Systems Ises 2023, 2023
Charge-plasma based symmetrical-gate complementary electron-hole bilayer TFET with improved performance for sub-0.5 V operation
Aadil Anam, Naveen Kumar, S Intekhab Amin, Dinesh Prasad, Sunny Anand
Semiconductor Science and Technology, 2023
Design and Analysis of GaSb/Si Based Negative Capacitance TFET at the Device and Circuit Level
Mohd Anas, S. Intekhab Amin, Mirza Tariq Beg, Aadil Anam, Ankush Chunn, Sunny Anand
Silicon, 2022
Simulation study and comparative analysis of proposed novel hybrid DG-TFET with conventional TFETs structures for improved performance
Aadil Anam, S. Intekhab Amin, Dinesh Prasad
Proceedings 2021 IEEE International Symposium on Smart Electronic Systems Ises 2021, 2021
Design and Performance Analysis of Tunnel Field Effect Transistor with Buried Strained Si1-xGexSource Structure Based Biosensor for Sensitivity Enhancement
Aadil Anam, Sunny Anand, S. Intekhab Amin
IEEE Sensors Journal, 2020

RECENT SCHOLAR PUBLICATIONS

Electro-thermal and switching performance of a heteroepitaxial π-Gate β-Ga₂O₃ MOSFET on a 4H-SiC substrate
MZ Alam, IA Khan, SI Amin, A Anam
Micro and Nanostructures 216, 208710 , 2026
2026
Design and Analysis of Mg2Si Source Based Vertical Quantum Tunneling Transistor to Enhance DC Switching Performance and its Application as Biosensors
M Raza, IA Khan, M Nizamuddin, A Anam
Silicon, 1-17 , 2026
2026
Electro-Thermal and Switching application of a Heteroepitaxial π-Gate β-Ga2O3 MOSFET on 4H-SiC
MZ Alam, IA Khan, SI Amin, A Anam
Micro and Nanostructures, 208710 , 2026
2026
Heteroepitaxial β‐Ga 2 O 3 Trench‐Gate MOSFET on 4H‐SiC: Trap, Thermal, and Breakdown Optimization
MZ Alam, IA Khan, SI Amin, A Anam
physica status solidi (a) 223 (7), e202500848 , 2026
2026
β -Ga 2 O 3 trench-gate MOSFET with VLD and field plate design for enhanced RF, thermal, breakdown voltage, and switching application
MZ Alam, IA Khan, SI Amin, A Anam
Physica Scripta 101 (1), 015004 , 2026
2026
Citations: 1
Cryogenic and Quantum Simulation of Short Channel 30 nm SOI MOSFET: An NEGF Quantum Simulation
A Anam, SI Amin, D Prasad
Silicon 17 (17), 4191-4207 , 2025
2025
Science and Technology of Tunnel Field‐Effect Transistors
Z Rasool, N Yousf, A Anam, SI Amin
Field Effect Transistors, 157-187 , 2025
2025
Citations: 1
Design and Analysis of High‐Performance Schottky Barrier β‐Ga 2 O 3 MOSFET With Enhanced Drain Current, Breakdown Voltage, and PFOM
MZ Alam, IA Khan, SI Amin, A Anam, MT Beg
International Journal of Numerical Modelling: Electronic Networks, Devices … , 2025
2025
Citations: 8
III-V material-based junction-free L-shaped gate normal line tunneling FET for improved performance
A Anam, SI Amin, D Prasad
Semiconductor Science and Technology 39 (9), 095004 , 2024
2024
Citations: 1
Novel III-V inverted T-channel TFET with dual-gate impact on line tunneling, with and without negative capacitance
A Anam, SI Amin, D Prasad
Microelectronics Journal 151, 106309 , 2024
2024
Citations: 9
Optimizing InGaAs/GaAsSb Staggered Bandgap U-Gate Line TFET With p + -Pocket Implant and Negative Capacitance for Enhanced Performance
A Anam, SI Amin, D Prasad
IEEE Transactions on Nanotechnology 23, 584-590 , 2024
2024
Citations: 7
Raised Ge-Source with n+ pocket and recessed drain line TFET: A proposal for biosensing applications
A Anam, SI Amin, D Prasad
Materials Science and Engineering: B 306, 117456 , 2024
2024
Citations: 5
Ultralow-Power DST-TFET pH Sensor Exceeding the Nernst Limit with Influence of Temperature on Sensitivity
N Yousf, A Anam, Z Rasool, SI Amin
ACS Applied Bio Materials 7 (7), 4562-4572 , 2024
2024
Citations: 4
Exploring Intertwined quantum and cryogenic behaviour in ultra-scaled 10 nm MOSFET: a NEGF quantum ballistic simulation
A Anam, SI Amin, D Prasad
Physica Scripta 99 (6), 065931 , 2024
2024
Citations: 2
InSb Source-Based Heterojunctionless Nanowire Tunneling FET for Biosensing Application: Design and Analysis
A Anam, SI Amin, D Prasad
2024 IEEE International Conference on Interdisciplinary Approaches in … , 2024
2024
Citations: 2
Performance Analysis of InSb Source-Based Heterojunctionless Nanowire TFET for Low-Power Application: Design and Simulation
A Anam, SI Amin, D Prasad
2024 IEEE International Conference on Interdisciplinary Approaches in … , 2024
2024
Citations: 1
Effect of ambipolarity suppression in PNPN TFET with dopant segregated Schottky-drain technique
A Anam, SI Amin, D Prasad, N Kumar, S Anand
Microelectronics Journal 145, 106116 , 2024
2024
Citations: 20
Temperature Sensitivity and Reliability Study of Symmetrical U-Shaped Gate Line TFET: RF/Analog and Linearity Performance Analysis
A Anam, SI Amin, D Prasad
2023 IEEE International Symposium on Smart Electronic Systems (iSES), 99-104 , 2023
2023
Charge-plasma-based inverted T-shaped source-metal dual-line tunneling FET with improved performance at 0.5 V operation
A Anam, SI Amin, D Prasad, N Kumar, S Anand
Physica Scripta 98 (9), 095918 , 2023
2023
Citations: 21
Analysis of III-V material-based dual source T-channel junction-less TFET with metal implant for improved DC and RF performance
A Anam, SI Amin, D Prasad, N Kumar, S Anand
Micro and Nanostructures 181, 207629 , 2023
2023
Citations: 25

MOST CITED SCHOLAR PUBLICATIONS

Design and Performance Analysis of Tunnel Field Effect Transistor With Buried Strained Si 1− x Ge x Source Structure Based Biosensor for Sensitivity Enhancement
A Anam, S Anand, SI Amin
IEEE Sensors Journal 20 (22), 13178-13185 , 2020
2020
Citations: 118
Analysis of III-V material-based dual source T-channel junction-less TFET with metal implant for improved DC and RF performance
A Anam, SI Amin, D Prasad, N Kumar, S Anand
Micro and Nanostructures 181, 207629 , 2023
2023
Citations: 25
Charge-plasma based symmetrical-gate complementary electron–hole bilayer TFET with improved performance for sub-0.5 V operation
A Anam, N Kumar, SI Amin, D Prasad, S Anand
Semiconductor Science and Technology 38 (1), 015012 , 2023
2023
Citations: 23
Charge-plasma-based inverted T-shaped source-metal dual-line tunneling FET with improved performance at 0.5 V operation
A Anam, SI Amin, D Prasad, N Kumar, S Anand
Physica Scripta 98 (9), 095918 , 2023
2023
Citations: 21
Effect of ambipolarity suppression in PNPN TFET with dopant segregated Schottky-drain technique
A Anam, SI Amin, D Prasad, N Kumar, S Anand
Microelectronics Journal 145, 106116 , 2024
2024
Citations: 20
Design and analysis of GaSb/Si based negative capacitance TFET at the device and circuit level
M Anas, SI Amin, MT Beg, A Anam, A Chunn, S Anand
Silicon 14 (17), 11951-11961 , 2022
2022
Citations: 14
Undoped vertical dual-bilayer TFET with a super-steep sub-threshold swing: proposal and performance comparative analysis
A Anam, SI Amin, D Prasad, N Kumar, S Anand
Semiconductor Science and Technology 38 (7), 075005 , 2023
2023
Citations: 11
Novel III-V inverted T-channel TFET with dual-gate impact on line tunneling, with and without negative capacitance
A Anam, SI Amin, D Prasad
Microelectronics Journal 151, 106309 , 2024
2024
Citations: 9
Design and Analysis of High‐Performance Schottky Barrier β‐Ga 2 O 3 MOSFET With Enhanced Drain Current, Breakdown Voltage, and PFOM
MZ Alam, IA Khan, SI Amin, A Anam, MT Beg
International Journal of Numerical Modelling: Electronic Networks, Devices … , 2025
2025
Citations: 8
Optimizing InGaAs/GaAsSb Staggered Bandgap U-Gate Line TFET With p + -Pocket Implant and Negative Capacitance for Enhanced Performance
A Anam, SI Amin, D Prasad
IEEE Transactions on Nanotechnology 23, 584-590 , 2024
2024
Citations: 7
Simulation study and comparative analysis of proposed novel hybrid DG-TFET with conventional TFETs structures for improved performance
A Anam, SI Amin, D Prasad
2021 IEEE International Symposium on Smart Electronic Systems (iSES), 311-315 , 2021
2021
Citations: 6
Raised Ge-Source with n+ pocket and recessed drain line TFET: A proposal for biosensing applications
A Anam, SI Amin, D Prasad
Materials Science and Engineering: B 306, 117456 , 2024
2024
Citations: 5
Ultralow-Power DST-TFET pH Sensor Exceeding the Nernst Limit with Influence of Temperature on Sensitivity
N Yousf, A Anam, Z Rasool, SI Amin
ACS Applied Bio Materials 7 (7), 4562-4572 , 2024
2024
Citations: 4
Exploring Intertwined quantum and cryogenic behaviour in ultra-scaled 10 nm MOSFET: a NEGF quantum ballistic simulation
A Anam, SI Amin, D Prasad
Physica Scripta 99 (6), 065931 , 2024
2024
Citations: 2
InSb Source-Based Heterojunctionless Nanowire Tunneling FET for Biosensing Application: Design and Analysis
A Anam, SI Amin, D Prasad
2024 IEEE International Conference on Interdisciplinary Approaches in … , 2024
2024
Citations: 2
β -Ga 2 O 3 trench-gate MOSFET with VLD and field plate design for enhanced RF, thermal, breakdown voltage, and switching application
MZ Alam, IA Khan, SI Amin, A Anam
Physica Scripta 101 (1), 015004 , 2026
2026
Citations: 1
Science and Technology of Tunnel Field‐Effect Transistors
Z Rasool, N Yousf, A Anam, SI Amin
Field Effect Transistors, 157-187 , 2025
2025
Citations: 1
III-V material-based junction-free L-shaped gate normal line tunneling FET for improved performance
A Anam, SI Amin, D Prasad
Semiconductor Science and Technology 39 (9), 095004 , 2024
2024
Citations: 1
Performance Analysis of InSb Source-Based Heterojunctionless Nanowire TFET for Low-Power Application: Design and Simulation
A Anam, SI Amin, D Prasad
2024 IEEE International Conference on Interdisciplinary Approaches in … , 2024
2024
Citations: 1
Electro-thermal and switching performance of a heteroepitaxial π-Gate β-Ga₂O₃ MOSFET on a 4H-SiC substrate
MZ Alam, IA Khan, SI Amin, A Anam
Micro and Nanostructures 216, 208710 , 2026
2026

Aadil Anam

RESEARCH, TEACHING, or OTHER INTERESTS

Scopus Publications

RECENT SCHOLAR PUBLICATIONS

MOST CITED SCHOLAR PUBLICATIONS