Dr. Soumen Mallick

Scopus Publications

Automated Design of CMOS-DACML Circuit
Soumen Mallick, Shibendu Mahata, Saikat Layek, Arinjoy Mitra, Bikram Rajak
2024 IEEE International Conference on Communication Computing and Signal Processing Iicccs 2024, 2024
This paper presents a new method for designing a differential amplifier using CMOS technology, incorporating a current mirror load (CMOS-DACML). To tackle the intricate optimization challenges presented by this nonlinear and multidimensional problem, the study utilizes a combined optimization strategy called fitness-based adaptive differential evolution with particle swarm optimization (ADEPSO). Through this hybrid approach, the design achieves substantial enhancements across critical performance metrics. Specifically, it achieves a notable reduction in power dissipation, lowering it to 520.60 µW. Moreover, the amplifier demonstrates a higher gain of 44.70 dB, significantly reduced output capacitance of 4.20 pF, and an enhanced cutoff frequency reaching 103.60 kHz. These outcomes highlight the effectiveness of ADEPSO in tackling the intricate challenges associated with differential amplifier design, especially in the context of CMOS-DACML. By optimizing these parameters simultaneously, the approach not only improves performance metrics but also underscores its potential for future applications in integrated circuit design and optimization.
A DVCC Based Realization of Optimized Fractional Step Low Pass Filter
Shibendu Mahata, Soumen Mallick, Rahul Kumar Tanti, Balaram Halder, Piyush Dutta, Subhajit Hati
2024 IEEE 2nd International Conference on Emerging Trends in Engineering and Medical Sciences Icetems 2024, 2024
Realization of fractional-step low-pass Butterworth filter (FSLBF) using a differential voltage current conveyor (DVCC) is presented. To approximate the FSLBF characteristic, the coefficients of three different filter transfer functions are optimally determined using the Craziness-based Particle Swarm Optimization (CRPSO) algorithm. Minimum absolute pole angle, −3 dB frequency response, squared magnitude error, etc., of the FSLBFs are evaluated. Simulations verify the efficacy of DVCC-based realizations for the designed frequency filters.
Optimal design of second generation current conveyor using craziness-based particle swarm optimisation
Soumen Mallick, Rajib Kar, Durbadal Mandal
International Journal of Bio Inspired Computation, 2022
In this paper, a population-based meta-heuristic search algorithm called craziness-based particle swarm optimisation (CRPSO) has been employed for the optimal design of positive second-generation current conveyor based on a trans-linear loop (CCII+). CRPSO accepts several random variables for encompassing improved and quicker search and utilisation in multidimensional search space. The main goal of this work is to optimally size the CCII+ building block to attain the suitable aspect ratios of the MOS transistors. To enhance the performance of a CCII+ design, it needs to increase the higher cut-off frequency of the current signal (fCI) as well as to decrease the input X-port parasitic resistance (RX). Accordingly, the optimisation problem is developed as a bi-objective problem of minimisation to obtain the least value of RX and the superior value of fCI. The current conveyor is simulated and validated using UMC 180 nm CMOS technology with a power supply of ±2.5 V in Cadence Virtuoso XL Design Environment.
Optimal design of 2.4 GHz CMOS LNA using PSO with aging leader and challenger
S. Mallick, R. Kar, D. Mandal, Tanya Dasgupta, S. P. Ghoshal
Advances in Intelligent Systems and Computing, 2019
This paper presents in front of us a novel approach for the optimal design of a Low Noise Amplifier (LNA) with inductive source degeneration circuit using a recently proposed evolutionary optimization technique called PSO with Aging Leader and Challenger (ALC-PSO). The proposed ALC-PSO based approach has succeeded in dealing with the disadvantages faced by PSO algorithm and is employed in this paper for the optimal design of LNA circuit. The MOSFET widths and component’s values are optimized by using ALC-PSO algorithm in order to maximize the gain, minimize the Noise Figure (NF) and to optimize the overall performance of the LNA circuit. The simulation results obtained for the designed LNA circuit confirm the effectiveness of the ALC-PSO based approach over PSO in terms of solution quality, design specifications, and design objectives. The optimally implemented LNA circuit in 0.35 µm CMOS technology yields the gain of 18.64 dB, noise figure of 1.779 dB and power dissipation of 10.60 mW.
Sizing of two stage op-Amp using OHS algorithm
Soumen Mallick, Kumari Suman, Rajib Kar, Durbadal Mandal, Sakti Prasad Ghoshal
2017 International Electrical Engineering Congress Ieecon 2017, 2017
An optimally designed CMOS Op-Amp has been presented in this article. Opposition concept based harmony Search (OHS) algorithm is applied for obtaining the minimum MOS area of the proposed Op-Amp. The proposed OHS based analog CMOS Op-Amp circuit design has alleviated from the problems of suboptimal convergence and stagnation, unlike Particle Swarm Optimization (PSO) and Harmony Search (HS). The least total MOS area of 121.8 μm2 is obtained in 0.35 μm CMOS technology with a power dissipation of 616.3 μW.
Optimal design of 5.5 GHz CMOS Lna using hybrid fitness based adaptive de with PSO
S. Mallick, J. R. Akhil, A. Dasgupta, Rajib Kar, Durbadal Mandal, Sakti Prasad Ghoshal
2017 International Electrical Engineering Congress Ieecon 2017, 2017
This paper presents a novel approach for the optimal design of a Low Noise Amplifier (LNA) with inductive source degeneration circuit using a novel hybrid optimization technique called fitness based adaptive differential evolution with particle swarm optimization (ADEPSO). The simulation results obtained for the designed LNA confirm the effectiveness of the ADEPSO based approach over PSO in terms of the solution quality, design specifications and design objectives. The optimally designed CMOS LNA circuit implemented in 0.18 μm CMOS technology yields a gain of 22.11 dB and the noise figure of 0.799 dB and the power dissipation of 6.6 mW.
Optimal sizing of CMOS analog circuits using gravitational search algorithm with particle swarm optimization
S. Mallick, R. Kar, D. Mandal, S. P. Ghoshal
International Journal of Machine Learning and Cybernetics, 2017
In this paper, a hybrid population based meta-heuristic search algorithm named as gravitational search algorithm (GSA) combined with particle swarm optimization (PSO) (GSA–PSO) is proposed for the optimal designs of two commonly used analog circuits, namely, complementary metal oxide semiconductor (CMOS) differential amplifier circuit with current mirror load and CMOS two-stage operational amplifier circuit. PSO and GSA are simple, population based robust evolutionary algorithms but have the problem of suboptimality, individually. The proposed GSA–PSO based approach has overcome this disadvantage faced by both the PSO and the GSA algorithms and is employed in this paper for the optimal designs of two amplifier circuits. The transistors’ sizes are optimized using GSA–PSO in order to minimize the areas occupied by the circuits and to improve the design/performance parameters of the circuits. Various design specifications/performance parameters are optimized to optimize the transistor’s sizes and some other design parameters using GSA–PSO. By using the optimal transistor sizes, Simulation Program with Integrated Circuit Emphasis simulation has been carried out in order to show the performance parameters. The simulation results justify the superiority of GSA–PSO over differential evolution, harmony search, artificial bee colony and PSO in terms of convergence speed, design specifications and performance parameters of the optimal design of the analog CMOS amplifier circuits. It is shown that GSA–PSO based design technique for each amplifier circuit yields the least MOS area, and each designed circuit is shown to have the best performance parameters like gain, power dissipation etc., as compared with those of other recently reported literature. Still the difficulties and challenges faced in this work are proper tuning of control parameters of the algorithms GSA and PSO, some conflicting design/performance parameters and design specifications, which have been partially overcome by repeated manual tuning. Multi-objective optimization may be the proper alternative way to overcome the above difficulties.
SEOA-based optimal design of analogue CMOS amplifier circuits
Soumen Mallick, Rajib Kar, Sakti Prasad Ghoshal, Durbadal Mandal
International Journal of Bio Inspired Computation, 2017
This paper presents social emotional optimisation algorithm (SEOA) based optimal designs of two analogue CMOS amplifier circuits. In SEOA, human behaviour is organised for attaining superior position in society. The person with the topmost position in society provides the optimal solution in multi-dimensional search space in this virtual world. To earn the supreme position in society through the assistance and rivalry with others not only results in better exploration and exploitation of problem space but also ensures faster convergence to optimal solution. The transistors' sizes are optimised to minimise the total MOS occupied area with better performance parameters of the circuits. The simulation results prove that the efficiency of the proposed SEOA-based approach over DE, harmony search (HS), artificial bee colony (ABC) and PSO in terms of convergence speed, specifications of design parameters and yields the least MOS area with improved gain and lower power dissipation.
CMOS analog amplifier circuit sizing using opposition based harmony search algorithm
S. Mallick, K. Sudhakar, R. Kar, D. Mandal, S. P. Ghoshal
International Conference on Communication and Signal Processing Iccsp 2016, 2016
An optimum design of analog CMOS differential amplifier (Diff-Amp) with current mirror load has been presented in this paper. An evolutionary optimization technique called Opposition based Harmony Search Algorithm (OHS) is employed to minimize the total MOSFET area of the designed circuit. The novel Harmony Search (HS) algorithm is selected as the parent and the opposition based approach is employed to it with an intention to exhibit accelerated near-global convergence profile. At the initialization stage, for choosing the randomly generated population/solutions, opposite solutions are also considered and the fitter one is selected as apriori guess. This causes faster convergence profile. Each solution in Harmony Memory (HM) is generated on the basis of memory consideration rule, a pitch adjustment rule and a re-initialization process which gives the optimum result corresponding to the least error fitness in multidimensional search space. Differential Evolution (DE), Harmony Search (HS), Artificial Bee Colony (ABC) and Particle Swarm Optimization (PSO) have an inbuilt disadvantage of early convergence and stagnation problem. But in OHS optimization technique has overcome these shortcomings. The optimally designed differential amplifier circuit occupies the least total MOS area, and shows the best design conditions like gain, power dissipation etc., in comparison with the formerly reported literature.
Optimal sizing and design of CMOS analogue amplifier circuits using craziness-based particle swarm optimization
S. Mallick, R. Kar, S. P. Ghoshal, D. Mandal
International Journal of Numerical Modelling Electronic Networks Devices and Fields, 2016
This paper presents the optimal designs of two analogue complementary metal-oxide-semiconductor CMOS amplifier circuits, namely differential amplifier with current mirror load and two-stage operational amplifier. A modified Particle Swarm Optimization PSO, called Craziness-based Particle Swarm Optimization CRPSO technique is applied to minimize the total MOS area of the designed circuits. CRPSO is a highly modified version of conventional PSO, which adopts a number of random variables and has a better and faster exploration and exploitation capability in the multidimensional search space. Integration of craziness factor in the fundamental velocity term of PSO not only brings diversity in particles but also pledges convergence close to global best solution. The proposed CRPSO-based circuit optimization technique is reassured to be free from the intrinsic disadvantages of premature convergence and stagnation, unlike Differential Evolution DE, Harmony Search HS, Artificial Bee Colony ABC and Particle Swarm Optimization PSO. The simulation results achieved for the two analogue CMOS amplifier circuits establish the efficacy of the proposed CRPSO-based approach over those of DE, HS, ABC and PSO in terms of convergence haste, design conditions and design goals. The optimally designed analogue CMOS amplifier circuits occupy the least MOS area and show the best performance parameters like gain and power dissipation, in compared with the other reported literature. Copyright © 2016 John Wiley & Sons, Ltd.
CMOS analogue amplifier circuits optimisation using hybrid backtracking search algorithm with differential evolution
S. Mallick, R. Kar, D. Mandal, S.P. Ghoshal
Journal of Experimental and Theoretical Artificial Intelligence, 2016

Dr. Soumen Mallick

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