Janamani Chandram Ayyangalam

@gitam.edu

Assitant Professor and Electrical, Electronics, and Communication Engineering
GITAM Deemed to be University

Janamani Chandram Ayyangalam


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https://researchid.co/janamani

RESEARCH, TEACHING, or OTHER INTERESTS

Electrical and Electronic Engineering
1

Scopus Publications

1

Scholar Citations

1

Scholar h-index

Scopus Publications

  • Optimization of CMOS compatible non-perovskite ferroelectric gate stack for designing low power Ferroelectric tunnel FETs
    Venkata Apparao Yempada, Srivatsava Jandhyala, Janamani Chandram Ayyangalam
    2024 28th International Symposium on VLSI Design and Test Vdat 2024, 2024
    Integration challenges of perovskites-based ferroelectrics increased the focus on usage of non-perovskites for the design of Negative Capacitance (NC) FETs. To meet the sub-60mV/decade subthreshold swing without compromising the on-state performance in advanced nodes, integration of Ferroelectric layer in the gate stack of a lateral Heterojunction Tunnel FET(HTFET) is an optimum choice. Ferroelectric materials when stabilized, exhibit hysteresis-free negative capacitance characteristics that improve the subthreshold swing and thereby the on-state performance TFET. In this work we explored the CMOS compatible non-perovskites based ferroelectrics, such as doped Hafnium oxide (HfO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>), and Hafnium Zirconium oxide (HZO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>), for designing Staggered gap Heterojunction Ferroelectric TFETs(He-FeTFET), for low power logic applications. Using SILVACO TCAD, a commercial Technology CAD software, an exhaustive simulation study is made tuning the device parameters, to achieve a hysteresis-free steeper switching with sub-60 mV/decade subthreshold swing without compromising the on-state performance and to achieve very low leakage, of the order of sub-fA. The material system, dopings of the device and the thickness of the ferroelectric layer, necessary to achieve a point subthreshold-swing of lesser than 10 mV/decade and large on-to-off current ratio (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf>/I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf>) ≈ 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> for the He-FeTFET are presented and performance is compared with a plain HTFET.

RECENT SCHOLAR PUBLICATIONS

  • > Optimization of CMOS compatible non-perovskite ferroelectric gate stack for designing low power Ferroelectric tunnel FETs
    VA Yempada, S Jandhyala, JC Ayyangalam
    2024 28th International Symposium on VLSI Design and Test (VDAT), 1-5 , 2024
    2024
    Citations: 1

MOST CITED SCHOLAR PUBLICATIONS

  • > Optimization of CMOS compatible non-perovskite ferroelectric gate stack for designing low power Ferroelectric tunnel FETs
    VA Yempada, S Jandhyala, JC Ayyangalam
    2024 28th International Symposium on VLSI Design and Test (VDAT), 1-5 , 2024
    2024
    Citations: 1