SUNIL RATHORE

@manipal.edu

Assistant Professor and School of Electrical Engineering
Manipal Institute of Technology Manipal, Karnataka

SUNIL RATHORE


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https://researchid.co/sunil140790

RESEARCH, TEACHING, or OTHER INTERESTS

Engineering, Electrical and Electronic Engineering
50

Scopus Publications

Scopus Publications

  • Demonstrating the Electro-Thermal Dynamics in Complementary FETs: Quantifying the Role of Self-Heating and Grain Effect Intercoupling
    Sandeep Kumar, Deven H. Patil, Sunil Rathore, S. Dasgupta, Navjeet Bagga
    IEEE Transactions on Electron Devices, 2026
    The vertical stacking of sheets and separating them by a dielectric raises severe thermal and geometrical reliability concerns in the complementary field effect transistor (CFET). Using well-calibrated TCAD models, we investigated the impact of the self-heating effect (SHE) and the role of dielectric separation wall (D<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SW</sub>) in electro-thermal coupling. The resulting thermal crosstalk due to D<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SW</sub> shows an increase in temperature of 2.09% (1.60%) at the pFET (nFET) when nFET (pFET) is in the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> state. Furthermore, the metal grain granularity (MGG) is a vital factor that affects the electro-thermal characteristics. It offers the randomized metal work function (WF), thereby significantly causing the shift in threshold voltage (V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub>). A semi-empirical model is proposed to define the ratio of effective grain size to gate (RGG) area, which provides insight into the grain boundaries and their optimization in CFET. In addition, the significance of the extension region (L<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EXT</sub>) in electro-thermal performance is explored, as L<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EXT</sub> offers series resistance, which modulates thermal resistance. The increase in L<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EXT</sub> from 3 to 7 nm results in decreased lattice temperature (T<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub>) by ~29 K; however, it increases the series resistance and causes the decrease in <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> current (I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub>) by 28% (25%) in nFET (pFET). At last, we predicted the device’s lifetime based on V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift (i.e., change in V<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\text {th}}= \pm 50$</tex-math> </inline-formula> mV). Thus, the proposed analysis is worth exploring for the reliability-aware CFET design in sub-3 nm nodes.
  • A Novel Latch Reset Technique Enabling Sub- 6 μ ~W Operation in Double-Tail Comparator
    Aditya Dubey, Sunil Rathore, Navjeet Bagga
    Proceedings 2026 39th International Conference on VLSI Design and 25th International Conference on Embedded Systems Vlsid 2026, 2026
    The comparators are crucial components in data converters, e.g., analog-to-digital converters (ADCs), sensors, and control systems to enable rapid binary decisions derived from specific thresholds in analog signals. This paper proposes a novel latch reset technique for a double-tail comparator to attain lowpower operations. To reset the latch, the additional pull-up (PMOS) transistors are included in the pre-amplifier stage, which are switched by the derived clock signal (MCLKB) from the baseline clock (CLK). The delayed version, i.e., MCLKB, resets the latch to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{D d}$</tex>. Therefore, the proposed method enhances the energy efficiency of the comparator by minimizing dynamic power consumption. Using optimized timing and control of the latch stage, the simulation has been performed for the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{4 5 ~ n m}$</tex> CMOS process, demonstrating that the comparator achieves a power consumption of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5.85 \mu ~\mathrm{W}$</tex> at a 1 V supply. Monte-Carlo simulation has been done for 200 samples, showing the average power distribution with a standard deviation of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.8 \mu ~\mathrm{W}$</tex>. The effective layout area of the proposed design is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$60 \mu ~\mathrm{m}^{2}$</tex>. Thus, the proposed technique is needed to design the low-power analog front ends.
  • Statistical Analysis of Metal Grain Granularities Induced Variability in 4T Complementary FET SRAM Cell
    Deven H Patil, Sandeep Kumar, Sunil Rathore, S. Dasgupta, Navjeet Bagga
    10th IEEE Electron Devices Technology and Manufacturing Conference Emerging Semiconductor Devices and Manufacturing Technologies Edtm 2026, 2026
    Complementary FETs (CFETs) vertically stack n– and p–FETs to achieve superior scaling; however, the confined gate metal thickness induces Metal Grain Granularity (MGG)–related workfunction fluctuations. Using well-calibrated TCAD simulations, this proposed study investigates: (i) the impact of MGG on threshold voltage deviation (σV<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf>), (ii) its influence on the static behavior of a 1T CFET inverter, and (iii) the resulting variability in the static noise margin (SNM) of a 4T CFET SRAM cell. The random grain orientations and boundaries yield σV<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> of ~10 mV (nFET) and ~9 mV (pFET), resulting in a ±13.2 mV shift in inverter switching threshold (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</inf>) for a 2 nm average grain size (G<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</inf>). Consequently, MGG-induced variability significantly degrades SRAM stability, with σSNM rising from 5 mV to 26.3 mV (Read) and from 8.3 mV to 39.7 mV (Hold) when G<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</inf> varied from 2 to 8nm. This indicates enhanced variability from reduced boundary averaging, with the Hold state showing greater deviation due to node isolation and positive feedback effects. Furthermore, histograms, QQ plots, and correlation plots have been used to determine the symmetry/non-symmetry of the left/right inverters in the designed 4T CFET SRAM cell. Thus, the proposed study provides a holistic insight into developing a variability-aware CFET SRAM cell.
  • Analytical Model of Resistivity Modulation and Assessing Temporal Dynamics of Complementary FET influenced by α-Particle Radiation
    Sandeep Kumar, Khushi Jain, Deven H Patil, Sunil Rathore, S. Dasgupta, Navjeet Bagga
    10th IEEE Electron Devices Technology and Manufacturing Conference Emerging Semiconductor Devices and Manufacturing Technologies Edtm 2026, 2026
    The high-energy radiation causes severe reliability and operational challenges in logic devices, as it generates electron-hole pairs (EHPs) upon colliding with the device and alters its effective resistivity/conductivity. This work proposes an analytical model for resistivity modulation and temporal analysis of Complementary FET (CFET) affected by α-particle radiation. In a well-calibrated TCAD setup, the device under test (DUT) is designed and exposed to a 500keV α-particle at different regions. The peak activation of EHP is observed when a strike happens at the drain extension region (D<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EXT</inf>). In addition, the angle of incidence (AoI) plays a crucial role in EHP generation/recombination (e.g., an AoI of 90° at D<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EXT</inf> leads to a 14.68% increase in OFF current compared to an AoI of 30°). The linear energy transfer (LET) effects are confirmed as the total current density increases by 0.87 kA/cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> when the radiation energy increases from 100 keV to 500 keV. To capture the resistivity modulation due to α-radiation, we proposed an analytical model for CFET resistance using the transmission line method (TLM). The proposed model aligns with TCAD results within < 5% error, establishing a reliable framework for investigating the α-radiation-induced reliability concerns in CFET technology.
  • Unveiling Gate Leakage Dynamics in Nanosheet FETs at Cryogenic Temperature: A TCAD Study
    Prabhat Singh, Malvika, Mohd. Shakir, Sandeep Kumar, Sunil Rathore, Navjeet Bagga, S. Dasgupta
    10th IEEE Electron Devices Technology and Manufacturing Conference Emerging Semiconductor Devices and Manufacturing Technologies Edtm 2026, 2026
    In this paper, we investigate the gate-leakage mechanism at cryogenic temperature (CT) in the Nanosheet FET (NSFET) using well-calibrated TCAD models. Using the Global TCAD Solution (GTS) tool, the carrier transport at cryogenic temperatures could be precisely captured by the Quasi-Fermi Transport (QFT) model. However, for evaluating gate leakage or OFF current, two possible models are available, i.e., the Tsu-Esaki and Fowler-Nordheim models, which require careful attention for accurate simulation. Thus, this study aims to explore the underlying behavior of the Cryo-NSFET characteristics with an appropriate modeling setup. As the temperature decreases to a deep-cryogenic range, the Fermi-Dirac distribution, i.e., the Fermi tail, becomes narrower, implying that fewer carriers have high energy, and thermal-assisted tunneling decreases. This results in a reduction in gate leakage current at all gate voltages. Our findings indicate that under CT, the absence of thermal excitation results in a shift in the transport mechanism to quantum tunneling. Additionally, gate tunneling is enhanced by a higher drain bias, which allows for the control of the potential barrier profile.
  • On the Reliability of Complementary Field Effect Transistor: Unveiling the Role of Grain Granularities and Random Fluctuations
    Sandeep Kumar, Deven H Patil, Sunil Rathore, Ankit Dixit, Naveen Kumar, Vihar Georgiev, S. Dasgupta, Navjeet Bagga
    IEEE Transactions on Device and Materials Reliability, 2026
    This study presents a comprehensive statistical reliability analysis of monolithic Complementary Field Effect Transistors (CFETs), focusing on the impact of process-induced variations. The analysis highlights key sources of variability, including Metal Gate Granularity (MGG), Poly Grain Granularity (PGG), Random Dopant Fluctuation (RDF), and Line Edge Roughness (LER). In smaller geometries, the gate metal (or poly-gate) grain granularities play a significant role in threshold voltage (V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub>) variations, raising severe reliability concerns. Through calibrated statistical TCAD simulations, the ON current (I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub>) variation of 2.82 μA (2.85 μA) is observed in the nFET (pFET) side of CFET, due to MGG for experimentally reported 5 nm grain size. In advanced technologies like high bandwidth memory (HBM), the gate is made of polysilicon that suffers from the PGG in sub-3 nm node devices. The observed coefficient-of-variance (CV) of pFET (2.19) is higher than nFET (1.45), which shows higher variability in pFET due to poly grain size variations. Further, the process-induced RDF and LER significantly alter the V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub>. Random numbers are generated by doping atoms in the Voronoi volume of each vertex to quantify the undoped and doped channels to statistically analyze the RDF. In contrast to a doped channel with σV<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> of 9 mV (7 mV) for nFET (pFET), the undoped scenario yields a default standard deviation (σV<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub>) of 2 mV. To characterize LER, correlation length (Λ) is a prime factor; as Λ approaches the sheet width, CV increases by 24.32% (37.22%) in nFET (pFET). Thus, the results underscore the need for stringent control over grain morphology, doping precision, and edge definition to ensure reliable CFET performance.
  • Analytical Model of Subthreshold Swing for Cryogenic-CMOS Considering Temperature Dependent Slope Factor
    Mohd. Shakir, N. Bagga, Y. Tiwari, Malvika, P. Singh, S. Rathore, S. Ranjan, S. Dasgupta
    10th IEEE Electron Devices Technology and Manufacturing Conference Emerging Semiconductor Devices and Manufacturing Technologies Edtm 2026, 2026
    Assessing the subthreshold behavior of the transistor is crucially important at cryogenic temperatures for the realization of quantum-compatible electronics. In the cryogenic regime, traditional thermal models fail to capture anomalies in the subthreshold region, such as band-tail states, incomplete dopant ionization, source-to-drain tunneling (SDT), and interface traps, thereby strongly influencing the subthreshold swing (SS). This work presents a semi-empirical temperature-dependent slope factor (n) model for a 28nm industry-standard bulk MOSFET, capturing the combined effects of thermionic emission, trap-assisted conduction, and SDT. The calibration and validation of the model are performed using the GTS TCAD tool, with a temperature ranging from 298 to 4.2K. Moreover, the SS behavior of the baseline Cryo-CMOS is investigated with various parameters, including channel length, substrate doping, and oxide thickness, which gives a clear insight into the device design guidelines for deep-cryogenic temperatures.
  • Sensitivity Prediction of a Hetero-Dielectric BioTFET Using ARIMA Model with Limited Dataset
    Karishma Nakhate, Sarthak S Sarda, Sankalp Dhandole, Chithraja Rajan, Meena Panchore, Sunil Rathore
    Silicon, 2025
  • Systematic performance benchmarking of nanosheet and FinFET: An intrinsic self-heating perspective
    Sunil Rathore, Rajeewa Kumar Jaisawal, Suneet Kumar Agnihotri, Navneet Gandhi, P.N. Kondekar, Navjeet Bagga
    Microelectronics Reliability, 2025
  • Self-Heating Induced Differential Resistance in Complementary FET: The Role of Dielectric Insulation in Thermal Dynamics
    Sandeep Kumar, Deven H. Patil, Sunil Rathore, S. Dasgupta, Navjeet Bagga
    IEEE Transactions on Dielectrics and Electrical Insulation, 2025
    The heat flux confined within the sheets or channels, i.e., between the gate dielectric and across the dielectric sidewall (D<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SW</sub>), engenders a severe self-heating effect (SHE) in stacked transistors like Complementary FETs (CFETs). This heat accumulation due to SHE reduces the velocity and mobility of charge carriers in the channel region, resulting in the negative differential resistance (NDR). This paper extensively provides insight into SHE in CFETs using a first-principles approach, i.e., from the fundamental current equation. In a conventional case, the carrier mobility, carrier concentration, velocity, and threshold voltage are temperature-dependent parameters; however, with SHE, the current (I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub>) is also drain-voltage (V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub>) dependent. Using well-calibrated TCAD models, we demonstrate the electrical and thermal characteristics of the CFET by extracting the I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> gradient as a function of temperature. We also investigated the CFET performance of the device under various parametric conditions, including channel width (W<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CH</sub>), channel thickness (T<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CH</sub>), and extension length (L<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EXT</sub>), and explained the significance of the dielectric layer in heat coupling across the D<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SW</sub>. The design guidelines for optimal W<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CH</sub>, T<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CH</sub>, and L<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EXT</sub> are presented, considering I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub>/C<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gg</sub> and intrinsic RC delay, as figure-of-merits. Henceforth, the proposed work underscores the importance of integrated electrical and thermal evaluations in establishing a robust framework for reliable and energy-efficient CFET architectures.
  • A Novel De-Mirroring Approach for Bias-dependent Capacitance Extraction in Nanosheet FET using Conformal Mapping
    Deven H Patil, Sandeep Kumar, Sunil Rathore, S. Dasgupta, Navjeet Bagga
    9th IEEE Electron Devices Technology and Manufacturing Conference Shaping the Future with Innovations in Devices and Manufacturing Edtm 2025, 2025
  • A Novel De-Mirroring-based Analytical Model for Capacitance Extraction of Nanosheet FET using Dielectric Permittivity Suppression
    Deven H Patil, Sandeep Kumar, Sunil Rathore, S. Dasgupta, Navjeet Bagga
    IEEE Transactions on Dielectrics and Electrical Insulation, 2025
  • The Role of Dielectric Wall in Forksheet FET: Exploring Electrical-Thermal Intercoupling
    Sunil Rathore, Navjeet Bagga, R. K. Jaisawal, Sandeep Kumar, M. Shakir, S. Dasgupta
    IEEE Transactions on Dielectrics and Electrical Insulation, 2025
  • Revealing the Reliability Performance of a Dielectric-Modulated Negative Capacitance Junctionless FinFET Biosensor
    Navneet Gandhi, Sunil Rathore, Rajeewa Kumar Jaisawal, P. N. Kondekar, Ankit Dixit, Naveen Kumar, Vihar Georgiev, Navjeet Bagga
    IEEE Transactions on Dielectrics and Electrical Insulation, 2025
  • Self-heating and Process Induced Performance Barrier on Complementary Field Effect Transistor: A Reliability Perspective
    Sandeep Kumar, Deven H Patil, Khushi Jain, Ankit Dixit, Sunil Rathore, Mohd. Shakir, Naveen Kumar, Vihar Georgiev, S. Dasgupta, Navjeet Bagga
    9th IEEE Electron Devices Technology and Manufacturing Conference Shaping the Future with Innovations in Devices and Manufacturing Edtm 2025, 2025
  • Unveiling the reliability of negative capacitance FinFET with confrontation of different HfO2-ferroelectric dopants
    Rajeewa Kumar Jaisawal, Sunil Rathore, P.N. Kondekar, Navjeet Bagga
    Solid State Electronics, 2024
  • A proof of concept for reliability aware analysis of junctionless negative capacitance FinFET-based hydrogen sensor
    Navneet Gandhi, Rajeewa Kumar Jaisawal, Sunil Rathore, P N Kondekar, Navjeet Bagga
    Smart Materials and Structures, 2024
  • Self-Heating and Process-Induced Threshold Voltage Aware Reliability and Aging Analysis of Forksheet FET
    Sunil Rathore, Navjeet Bagga, S. Dasgupta
    IEEE International Reliability Physics Symposium Proceedings, 2024
  • Unveiling the Role of Interface and Dielectric Wall Traps with Self-heating Induced Aging Prediction of Forksheet FET
    Sunil Rathore, Sandeep Kumar, Mohd. Shakir, Navjeet Bagga, S. Dasgupta
    IEEE Electron Devices Technology and Manufacturing Conference Strengthening the Globalization in Semiconductors Edtm 2024, 2024
  • TG-in-DRAM: A Transmission Gate based Full Adder using Multi-row Activation for enhanced Throughput in CIM Architectures
    Sambhav Sharma, Garima Choudhary, Neha Gupta, Sunil Rathore, Anand Bulusu, Sudeb Dasgupta
    Apccas and Primeasia 2024 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics Proceeding, 2024
  • Sensitivity and Reliability Assessment of a Strained Silicon Junctionless FinFET-based Hydrogen Gas Sensor
    Navneet Gandhi, Sunil Rathore, Rajeewa Kumar Jaisawal, P. N. Kondekar, Naveen Kumar, Ankit Dixit, Vihar Georgiev, Navjeet Bagga
    2024 IEEE Latin American Electron Devices Conference Laedc 2024, 2024
  • Revealing the Noise Dependent Sensitivity of a Junctionless FinFET-Based Hydrogen Sensor with Ferroelectric Gate Stack
    Navneet Gandhi, Sunil Rathore, Rajeewa Kumar Jaisawal, P. N. Kondekar, Naveen Kumar, Ankit Dixit, Vihar Georgiev, Navjeet Bagga
    International Conference on Simulation of Semiconductor Processes and Devices SISPAD, 2024
  • Recent challenges in the IT and semiconductor industry: From Von Neumann architecture to the future
    Young Suh Song, Shiromani Balmukund Rahi, Navjeet Bagga, Sunil Rathore, Rajeewa Kumar Jaisawal, P. Vimala, Neha Paras, K. Srinivasa Rao
    Negative Capacitance Field Effect Transistors Physics Design Modeling and Applications, 2023
  • Investigation of Analog/RF and linearity performance with self-heating effect in nanosheet FET
    Sunil Rathore, Rajeewa Kumar Jaisawal, Pravin N. Kondekar, Navjeet Bagga
    Microelectronics Journal, 2023
  • Unveiling the Self-Heating and Process Variation Reliability of a Junctionless FinFET-Based Hydrogen Gas Sensor
    Navneet Gandhi, Sunil Rathore, Rajeewa Kumar Jaisawal, P. N. Kondekar, Sayan Dey, Navjeet Bagga
    IEEE Sensors Letters, 2023
  • Demonstration of a Nanosheet FET With High Thermal Conductivity Material as Buried Oxide: Mitigation of Self-Heating Effect
    Sunil Rathore, Rajeewa Kumar Jaisawal, P. N. Kondekar, Navjeet Bagga
    IEEE Transactions on Electron Devices, 2023
  • Trap and self-heating effect based reliability analysis to reveal early aging effect in nanosheet FET
    Sunil Rathore, Rajeewa Kumar Jaisawal, P.N. Kondekar, Navjeet Bagga
    Solid State Electronics, 2023
  • Reliability of TCAD study for HfO2-doped Negative capacitance FinFET with different Material-Specific dopants
    Rajeewa Kumar Jaisawal, Sunil Rathore, P.N. Kondekar, Navjeet Bagga
    Solid State Electronics, 2023
  • Analog/RF and Linearity Performance Assessment of a Negative Capacitance FinFET Using High Threshold Voltage Techniques
    Rajeewa Kumar Jaisawal, Sunil Rathore, P. N. Kondekar, Navjeet Bagga
    IEEE Transactions on Nanotechnology, 2023
  • Demonstration of a Junctionless Negative Capacitance FinFET-based Hydrogen Gas Sensor: A Reliability Perspective
    Navneet Gandhi, Rajeewa Kumar Jaisawal, Sunil Rathore, P. N. Kondekar, Shashank Banchhor, Navjeet Bagga
    7th IEEE Electron Devices Technology and Manufacturing Conference Strengthen the Global Semiconductor Research Collaboration After the Covid 19 Pandemic Edtm 2023, 2023
  • Self-Heating Aware Threshold Voltage Modulation Conforming to Process and Ambient Temperature Variation for Reliable Nanosheet FET
    Sunil Rathore, Rajeewa Kumar Jaisawal, P. N. Kondekar, Navneet Gandhi, Shashank Banchhor, Young Suh Song, Navjeet Bagga
    IEEE International Reliability Physics Symposium Proceedings, 2023
  • Noise Analysis in FinFET-based Analog Circuit with Technology Scaling
    Mallikarjun Patil, Rajeewa Kumar Jaisawal, Shashank Banchhor, Navneet Gandhi, Navjeet Bagga, Sunil Rathore, P. N. Kondekar
    Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit Devic 2023, 2023
  • Self-Heating and Interface Traps Assisted Early Aging Revelation and Reliability Analysis of Negative Capacitance FinFET
    Rajeewa Kumar Jaisawal, Sunil Rathore, Navneet Gandhi, P. N. Kondekar, Shashank Banchhor, V Bharath Sreenivas, Young Suh Song, Navjeet Bagga
    7th IEEE Electron Devices Technology and Manufacturing Conference Strengthen the Global Semiconductor Research Collaboration After the Covid 19 Pandemic Edtm 2023, 2023
  • Analytical Model of Dual Cavity Nanowire Tunnel FET-based Dielectric Modulated Biosensor
    Saheli Sarkhel, Sunil Rathore, Priyanka Saha, Ankit Dixit, Taha Saquib, Rajeewa Kumar Jaisawal, P.N Kondekar, Navjeet Bagga
    Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit Devic 2023, 2023
  • Gate Oxide Induced Reliability Assessment of Junctionless FinFET-Based Hydrogen Gas Sensor
    Navneet Gandhi, Rajeewa Kumar Jaisawal, Sunil Rathore, P. N. Kondekar, Ankit Dixit, Navneen Kumar, Vihar Georgiev, Navjeet Bagga
    Proceedings of IEEE Sensors, 2023
  • Investigation of geometrical impact on a P+ buried negative capacitance SOI FET
    Toushik Santra, Ankit Dixit, Rajeewa Kumar Jaisawal, Sunil Rathore, Saheli Sarkhel, Navjeet Bagga
    Microelectronics Journal, 2022
  • Substrate BOX engineering to mitigate the self-heating induced degradation in nanosheet transistor
    Sunil Rathore, Rajeewa Kumar Jaisawal, Navneet Gandhi, P.N. Kondekar, Navjeet Bagga
    Microelectronics Journal, 2022
  • Role of temperature on linearity and analog/RF performance merits of a negative capacitance FinFET
    Rajeewa Kumar Jaisawal, Sunil Rathore, Navneet Gandhi, Pravin N Kondekar, Navjeet Bagga
    Semiconductor Science and Technology, 2022
  • Design Optimization of Three-Stacked Nanosheet FET From Self-Heating Effects Perspective
    Sunil Rathore, Rajeewa Kumar Jaisawal, Pravin N. Kondekar, Navjeet Bagga
    IEEE Transactions on Device and Materials Reliability, 2022
  • Investigation of ambient temperature and thermal contact resistance induced self-heating effects in nanosheet FET
    Sunil Rathore, Rajeewa Kumar Jaisawal, Preeti Suryavanshi, Pravin N Kondekar
    Semiconductor Science and Technology, 2022
  • Impact of Temperature on NDR Characteristics of a Negative Capacitance FinFET: Role of Landau Parameter (α)
    Rajeewa Kumar Jaisawal, Sunil Rathore, P. N. Kondekar, Navjeet Bagga
    Communications in Computer and Information Science, 2022
  • Role of Interfacial Oxide on Capacitance Matching in a Negative Capacitance FinFET: A Reliability Perspective
    Rajeewa Kumar Jaisawal, Sunil Rathore, Pravin N. Kondekar, Shashank Kumar Banchhor, Navjeet Bagga
    2022 IEEE International Conference on Emerging Electronics Icee 2022, 2022
  • Device Design Aware and Interface Thermal Resistance Assisted Self-Heating Analysis in Nanosheet FET
    Sunil Rathore, Shashank Kumar Banchhor, Rajeewa Kumar Jaisawal, Ankit Dixit, Pravin Kondekar, Navjeet Bagga
    2022 IEEE International Conference on Emerging Electronics Icee 2022, 2022
  • Insights into the operation of negative capacitance FinFET for low power logic applications
    Rajeewa Kumar Jaisawal, P.N. Kondekar, Sameer Yadav, Pranshoo Upadhyay, Bhaskar Awadhiya, Sunil Rathore
    Microelectronics Journal, 2022
  • Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques
    Rajeewa Kumar Jaisawal, Sunil Rathore, Pravin N Kondekar, Sameer Yadav, Bhaskar Awadhiya, Pranshoo Upadhyay, Navjeet Bagga
    Semiconductor Science and Technology, 2022
  • Silicide Ultrathin Impact Ionization MOS (SUTIMOS) for Ultra Low Power VLSI Application
    Ankit Dixit, Rajeewa Kumar Jaisawal, Sunil Rathore, Suneet Kumar Agnihotri, P.N. Kondekar
    Proceedings 2021 International Conference on Control Automation Power and Signal Processing Caps 2021, 2021
  • Effect of Scaling on Passive Voltage Amplification in FE-DE Hetero Structure
    Bhaskar Awadhiya, Pravin N. Kondekar, Sameer Yadav, Pranshoo Upadhyay, Rajeewa Kumar Jaisawal, Sunil Rathore
    Proceedings 2021 International Conference on Control Automation Power and Signal Processing Caps 2021, 2021
  • An Asynchronous Analog to Digital Converter for Video Camera Applications
    R. Sunil, R.K. Siddharth, Y.B. Nithin Kumar, M.H. Vasantha
    Proceedings of IEEE Computer Society Annual Symposium on VLSI Isvlsi, 2019
  • An asynchronous analog to digital converter for surveillance camera applications
    Siddharth R.K., Sunil R., Nithin Kumar Y.B., Vasantha M.H., Edoardo Bonizzoni
    Proceedings of IEEE Computer Society Annual Symposium on VLSI Isvlsi, 2018
  • Design and implementation of PID controller based on orthogonal wavelet filter-banks in FPGA
    Priyanandini Das, Pranose J Edavoor, Sithara Raveendran, Sunil Rathore, Amol D Rahulkar
    2017 7th International Symposium on Embedded Computing and System Design Ised 2017, 2017