Computer Engineering, Hardware and Architecture, Computer Science, Computational Theory and Mathematics
5
Scopus Publications
34
Scholar Citations
3
Scholar h-index
2
Scholar i10-index
Scopus Publications
Low Power Network-on-Chip Architecture Design Technique Tejas Musale, Arun Ganti, Ankur Gogoi, Kanchan Manna IEEE IFIP International Conference on VLSI and System on Chip VLSI Soc, 2024 In the evolving landscape of many-core architectures, the Network on Chip (NoC) emerges as a pivotal inter-connection framework, accommodating the escalating number of cores on a single chip. Despite its widespread adoption, power consumption remains a critical challenge, significantly influenced by factors such as topology, bit toggling, and routing algorithms, with bit-switching power being a predominant concern. In this work, we have proposed an innovative technique in the cores aimed at reducing the power consumption of the NoC. To calculate our method's area, time, and power consumption, we have synthesized it on a Xilinx Virtex-7 FPGA board. We have modified the Noxim open-source simulator to validate our approach using synthetic traffic. Empirical results demonstrate a 29.64% reduction in dynamic power consumption and a 29.09% improvement in switching activity for the average case (Mode 1) traffic scenario.
Application-driven fault identification in NoC designs Ankur Gogoi, Bibhas Ghoshal VLSI and Hardware Implementations Using Modern Machine Learning Methods, 2022 As System-on-Chip–based systems tend to become high performing, the intercore communication infrastructure such as Network-on-Chip (NoC) tends to become increasing fault prone. One of the major reasons for faults to occur in NoC is prolonged usage of the network. Out of all the components of the NoC, the routers are the most vulnerable to faults since they shoulder the maximum workload of the network. More the routers are in use, greater the chance of their wear out and in turn injection of faults. A mark of high usage of routers is increase in the workload or increased passing of flits through them. Faulty routers severely affect the performance of the system. Thus, it becomes imperative to detect these faults in the routers at an early stage, at best to predict their possibility before occurrence, in order to prevent disruption of system activities at a later stage. Since traffic movement through the NoC follows a specific pattern, the faulty router locations too vary with the traffic. Literature suggests that the state of the art approaches of faulty router detection in NoC assume fixed fault locations for all kinds of traffic patterns that move through the routers of the NoC. This assumption restricts the fault space and as a result the detection remains incomplete leading to inaccurate fault tolerant strategies. Thus, it becomes necessary to have a traffic dependent approach of detecting the probable faulty routers in NoC. The work presented in this chapter discusses an application-traffic–driven, fault-detection approach in NoC that makes use of machine learning strategy to identify faults in routers. Our work primarily targets MPSoC-based NoC architecture to ensure fault detection prior to traffic injection since the application traffic to be used is unknown during design time. The proposed methodology applies a phase-based technique of traffic classification (performed at an accuracy of 89.23%) and then identification of the faulty locations using a Look-up-Table (LuT)-based approach. We present both analytic- and simulation-based evaluation of the proposed methodology.
Application Phase Behavior-Guided Thermal Management of Embedded Platforms Rakesh Kumar, Akash Sachan, Ankur Gogoi, Bibhas Ghoshal IEEE Embedded Systems Letters, 2020 This letter presents a scheduling policy for multicore embedded applications based on their thermal phase behavior. The thermal phase-guided task allocation allows the scheduler to allocate tasks that run at elevated temperature to low-power cores while others running at normal temperature to high performing cores. The proposed phase-based thermal aware technique shows 15.4 °C reduction in average temperature and 30.5 °C in peak temperature when experimented with PARSEC benchmark applications targeted on the ODROID XU4 embedded platform.
RECENT SCHOLAR PUBLICATIONS
Low Power Network-on-Chip Architecture Design Technique T Musale, A Ganti, A Gogoi, K Manna 2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration … , 2024 2024 Citations: 1
Fault-aware routing approach for mesh-based Network-on-Chip architecture A Gogoi, B Ghoshal, K Manna Integration 93, 102043 , 2023 2023 Citations: 13
Application driven routing for mesh based network-on-chip architectures A Gogoi, B Ghoshal, A Sachan, R Kumar, K Manna Integration 84, 26-36 , 2022 2022 Citations: 14
Application-driven fault identification in NoC designs A Gogoi, B Ghoshal VLSI and Hardware Implementations using Modern Machine Learning Methods, 79-96 , 2021 2021 Citations: 1
Application phase behavior-guided thermal management of embedded platforms R Kumar, A Sachan, A Gogoi, B Ghoshal IEEE Embedded Systems Letters 12 (4), 121-124 , 2020 2020 Citations: 5
MOST CITED SCHOLAR PUBLICATIONS
Application driven routing for mesh based network-on-chip architectures A Gogoi, B Ghoshal, A Sachan, R Kumar, K Manna Integration 84, 26-36 , 2022 2022 Citations: 14
Fault-aware routing approach for mesh-based Network-on-Chip architecture A Gogoi, B Ghoshal, K Manna Integration 93, 102043 , 2023 2023 Citations: 13
Application phase behavior-guided thermal management of embedded platforms R Kumar, A Sachan, A Gogoi, B Ghoshal IEEE Embedded Systems Letters 12 (4), 121-124 , 2020 2020 Citations: 5
Low Power Network-on-Chip Architecture Design Technique T Musale, A Ganti, A Gogoi, K Manna 2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration … , 2024 2024 Citations: 1
Application-driven fault identification in NoC designs A Gogoi, B Ghoshal VLSI and Hardware Implementations using Modern Machine Learning Methods, 79-96 , 2021 2021 Citations: 1
