K V G SRINIVAS

@anits.edu.in

Assistant Professor
ANIL NEERUKONDA INSTITUTE OF TECHNOLOGY AND SCIENCES

K V G SRINIVAS


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https://researchid.co/srinu43306

RESEARCH INTERESTS

VLSI, SIGNAL PROCESSING
21

Scopus Publications

88

Scholar Citations

6

Scholar h-index

2

Scholar i10-index

Scopus Publications

  • Performance Optimized 32-bit Multiplier: Integrating Vedic and Karatsuba Techniques
    K. V. Gowreesrinivas, B. Vennela, L. Sasank, A. Sai Raghav, D. Venkata Satyanarayana
    Proceedings of 6th International Conference on 2025 Devices for Integrated Circuit Devic 2025, 2025
    Multiplication is a fundamental arithmetic operation widely used in applications like digital signal processing, cryptography, and control systems. This work presents a 32-bit hybrid multiplier that combines Vedic and Karatsuba algorithms to balance speed, area, and power consumption by leveraging the strengths of both methods. The hybrid architecture enhances computational efficiency, making it suitable for real-time applications. By integrating the benefits of Vedic and Karatsuba multipliers, the proposed design achieves optimal metrics in terms of power, speed, and area. Performance analysis shows that the hybrid multiplier reduces delay by 9.76% compared to the standalone Vedic multiplier and 7.94% compared to the Karatsuba multiplier, with minimal variation in power consumption. This makes the hybrid design ideal for high-performance digital systems, demonstrating its superiority over standalone designs in achieving an efficient trade-off across critical performance parameters.
  • Optimizing Power Consumption: CSD-Based 16-Bit Multiplier for Low-Power Systems
    K. V. Gowreesrinivas, S. Rahul, K. Arjun, B. Sushma, Ch. Mohan Sai
    Proceedings of 6th International Conference on 2025 Devices for Integrated Circuit Devic 2025, 2025
    This work introduces a new design of a 16-bit multiplier based on a Canonical Signed Digit (CSD) representation, optimized for low-power implementations. The design reduces switching activity by a great extent, which leads to a significant 99.4% power saving when compared to traditional Vedic multipliers. Reducing the number of non-zero bits in the CSD representation minimizes the number of partial products, which leads to reduced dynamic power consumption. Experimental results prove that the design reduces delay by 82%, with a competitive slice utilization. This work sets a new standard for energy-efficient multipliers, and it is suitable for resource-limited systems like IoT devices and real-time DSP applications.
  • Design And Implementation Of Power Efficient Multiplier Using Reversible Logic
    K. Yashoda, K V Gowreesrinivas, M Uma Mahesh, K S V L D Sai Phanindra, Aman Syed, S Sai
    Proceedings of 6th International Conference on 2025 Devices for Integrated Circuit Devic 2025, 2025
    In current VLSI Technology, Power Consumption has emerged as a very significant factor to consideration. The primary goal of this project is to design various bits of multiplier using reversible logic circuit with low Power Consumption. Here Power consumption is based on minimum Quantum cost. Lower the Quantum cost lower the Power Consumption. When designing reversible logic algorithms for multipliers, power consumption can be greatly optimized compared to conventional logic-based circuits. Reversible logic is defined by having an equal number of output lines and input lines. Reversible logic includes the use of reversible gates. There are several reversible logic gates, including the Fredkin Gate, Feynman Gate, Double Feynman Gate, Peres Gate, and Toffoli Gate. A comparative study is also given, considering garbage outputs, quantum cost, and the number of gates. Reversible logic is applied in embedded systems where power efficiency is important. In this Project, various bits of multipliers are designed using reversible logic. These circuits are optimized to have minimum quantum cost and produce the least number of garbage outputs.
  • FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders
    K. V. Gowreesrinivas, Sabbavarapu Srinivas, Punniakodi Samundiswary
    Engineering Technology and Applied Science Research, 2023
    Nowadays, the requirement for very high-speed operations in processors constantly increases. Multiplication is a crucial operation in high power-consuming processes such as image and signal processing. The main characteristics of a multiplier are good accuracy, speed, reduction in area, and little power consumption. Speed plays a major role in multiplication operations, and an increase in speed can be obtained by reducing the number of steps involved in the computation process. Since a multiplier has the largest delay among the basic blocks in a digital system, the critical path is determined by it. Furthermore, the multiplier consumes more area and dissipates more power. Hence, designing multipliers that offer high speed, lower power consumption, less area, or a combination of them is of prime concern. Hence, an attempt is made in this paper to achieve the above design metrics using a Spurious Power Suppression Technique (SPST) adder. A resource-efficient SPST-based Vedic multiplier is developed and implemented using Artix 7 FPGA and is finally compared with the ripple carry adder-based Vedic multiplier.
  • Design and Implementation of Hybrid Full Adder Based 16-bit Multiplication Using FPGA
    K.V. Gowreesrinivas, B.Usha Sri, S. Saideepak, G. Tarun, I.Sathya Sagar
    Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit Devic 2023, 2023
    In this paper 16-bit multiplication is implemented using higher order compressors such as 4:3, 5:3, 6:3,7:3, 8:4, 9:4, 10:4, 11:4, 15:4 and a higher order compressor based efficient 16-bit multiplier is proposed. Because of use of compressors, we obtain better area, better space than conventional multiplication. To further implementation of compressor-based multiplication, hybrid full adders are introduced by using Nand gates in our design. After introducing hybrid full adders better area, better space is obtained. In this, 16-bit multiplication using Wallace tree structure is developed. The Wallace tree method is applied to determine outcome of binary number multiplication. This approach transfers the result to the following stage after adding binary bits. Verilog HDL is used to implement every module, and Xilinx Vivado is used to create the synthesized modules.
  • FPGA Implementation of Area Efficient 16-Bit Vedic Multiplier Using Higher Order Compressors
    P Sairam, K Manikumar, Y Suresh Reddy, B Uday Narayana, K.V. Gowreesrinivas
    Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit Devic 2023, 2023
    The objective of this paper is to propose an 16-bit Vedic multiplier using higher order compressors. In Conventional multiplier, there are many partial steps which reduce the computational speed of a multiplier. Along with accuracy, the emphasis is on reducing processor area, power, and delay by increasing speed. Vedic mathematics rules and algorithms create partial products at the same moment, saving time. The performance of the multiplier in terms of latency, power, and area is found by the number of stages used to sum the partial products. In this paper, a novel Vedic multiplier architecture is presented that reduces area while increasing speed when compared to conventional Vedic multipliers. The suggested model is simulated and synthesized using Xilinx Vivado on different FPGA families and delay, area and power are observed. The conclusion drawn from observing the result is that implementation of multiplier using Virtex-6 (lower power) provides optimized outputs in terms of area, delay and power. The model is also implemented on Basys3 Artix7 FPGA with the help of Xilinx Vivado and verified the functionality of the proposed model.
  • Improvised hierarchy of floating point multiplication using 5:3 compressor
    K V Gowreesrinivas, Samundiswary P
    International Journal of Electronics Letters, 2022
    The main objective is to develop floating-point multiplication (FPM) using 5:3 compressor based Vedic multiplier (VM), Karatsuba algorithm (KA) and canonical signed digit (CSD) algorithm to overcome the drawbacks presented in conventional compressor based FPM. In this scenario, an attempt is made to enhance the performance of FPM using three efficient algorithms. Finally, the performance analysis in terms of area, delay and power dissipation of using VM, KA and CSD with 5:3 compressor are examined and compared. The designs f00which are involved in mantissa multiplication are coded in Verilog HDL and implemented using Xilinx Vivado. It is clearly convinced from the 5:3 compressor based CSD that it provides better performance than other two algorithms by achieving acceptable area and delay. Single precision floating point multiplication (SPFPM) using Vedic with 5:3 compressor requires 29% Look Up Table (LUT) area and 30% slice area improvement in comparing with KA. In case of delay, KA gives 35% improvement compared to vedic based SPFPM. For CSD algorithm based SPFPM requires 46% improvement in LUTs area and 49% improvement in Slice area compared to KA based SPFPM.
  • A Safe and Cost-Effective Algorithm for Automation of LPG Cylinder Booking Using ESP8266
    Srinivasa Naidu Nalla, K. V. Gowreesrinivas
    Lecture Notes in Electrical Engineering, 2021
  • Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba Algorithm
    K. V. Gowreesrinivas, P. Samundiswary
    Lecture Notes in Electrical Engineering, 2021
  • Multiplexer based high speed double precision floating point multiplication
    International Journal of Advanced Science and Technology, 2019
  • Area and delay efficient compressor based montgomery multiplier
    Ganesh Revathi, K V Gowreesrinivas, P. Samundiswary, S Khan, K Javeed, et al.
    International Journal of Engineering and Advanced Technology, 2019
  • High Speed Multipliers using Counters based on Symmetric Stacking
    Dathrak KavyaShree, P Samundiswary, K V Gowreesrinivas
    2019 International Conference on Computer Communication and Informatics Iccci 2019, 2019
  • Implementation and Analysis of Single Precision Floating Point Multiplication Using Vedic and Canonic Signed Digit Algorithm
    K V Gowreesrinivas, P. Samundiswary
    2018 9th International Conference on Computing Communication and Networking Technologies Icccnt 2018, 2018
  • Resource efficient single precision floating point multiplier using karatsuba algorithm
    Gowreesrinivas V K, Samundiswary P
    Indonesian Journal of Electrical Engineering and Informatics, 2018
  • Design and Analysis of Single Precision Floating Point Multiplication with Vedic Mathematics Using Different Techniques
    K. V. Gowreesrinivas, P. Samundiswary
    Lecture Notes in Electrical Engineering, 2018
  • FPGA implementation of single-precision floating point multiplication with karatsuba algorithm using vedic mathematics
    K. V. Gowreesrinivas, P. Samundiswary
    Smart Innovation Systems and Technologies, 2018
  • Design and analysis of single precision floating point multiplication using Karatsuba algorithm and parallel prefix adders
    K V Gowreesrinivas, P. Samundiswary
    2017 4th International Conference on Signal Processing Communication and Networking Icscn 2017, 2017
  • Comparative study on performance of single precision floating point multiplier using vedic multiplier and different types of adders
    K V Gowreesrinivas, P. Samundiswary
    2016 International Conference on Control Instrumentation Communication and Computational Technologies Iccicct 2016, 2017
  • Design and analysis of turbo encoder using Xilinx ISE
    Palle Prasanth Kumar, K V Gowreesrinivas, P Samundiswary
    2016 International Conference on Control Instrumentation Communication and Computational Technologies Iccicct 2016, 2017
  • Comparative analysis of single precision floating point multiplication using compressor techniques
    K. V. Gowreesrinivas, P. Samundiswary
    Proceedings of the 2017 International Conference on Wireless Communications Signal Processing and Networking Wispnet 2017, 2017
  • Comparative performance analysis of multiplexer based single precision floating point multipliers
    K V Gowreesrinivas, P Samundiswary
    Proceedings of the International Conference on Electronics Communication and Aerospace Technology Iceca 2017, 2017

RECENT SCHOLAR PUBLICATIONS

  • Design And Evaluation Of Energy-Efficient Approximate Multipliers
    PDP K V Gowreesrinivas , Ganesh Laveti, Chukka.Anoosha, Eswara Chaitanya ...
    International Journal of Environmental Sciences 11 (No. 16s), 2079-2089. , 2025
    2025
  • Design And Implementation Of Power Efficient Multiplier Using Reversible Logic
    K Yashoda, KV Gowreesrinivas, MU Mahesh, KS Phanindra, A Syed, ...
    2025 Devices for Integrated Circuit (DevIC), 390-395 , 2025
    2025
    Citations: 2
  • Optimizing Power Consumption: CSD-Based 16-Bit Multiplier for Low-Power Systems
    KV Gowreesrinivas, S Rahul, K Arjun, B Sushma, CM Sai
    2025 Devices for Integrated Circuit (DevIC), 407-411 , 2025
    2025
  • Performance Optimized 32-bit Multiplier: Integrating Vedic and Karatsuba Techniques
    KV Gowreesrinivas, B Vennela, L Sasank, AS Raghav, ...
    2025 Devices for Integrated Circuit (DevIC), 132-137 , 2025
    2025
  • FPGA implementation of a resource efficient vedic multiplier using SPST adders
    KV Gowreesrinivas, S Srinivas, P Samundiswary
    Engineering, Technology & Applied Science Research 13 (3), 10698-10702 , 2023
    2023
    Citations: 12
  • Design and implementation of hybrid full adder based 16-bit multiplication using FPGA
    KV Gowreesrinivas, BU Sri, S Saideepak, G Tarun, IS Sagar
    2023 IEEE Devices for Integrated Circuit (DevIC), 451-454 , 2023
    2023
    Citations: 3
  • Fpga implementation of area efficient 16-bit vedic multiplier using higher order compressors
    P Sairam, K Manikumar, YS Reddy, BU Narayana, KV Gowreesrinivas
    2023 IEEE Devices for Integrated Circuit (DevIC), 404-407 , 2023
    2023
    Citations: 6
  • Improvised hierarchy of floating point multiplication using 5: 3 compressor
    KV Gowreesrinivas, S P
    International Journal of Electronics Letters 10 (1), 87-100 , 2022
    2022
    Citations: 3
  • BI Histogram Equalization Based Image Enhancement with Bicubic Interpolation
    BSJ J Bhaskara Raoa*, K V G Srinivasb, A Siva Kumarc
    Jana Bhaskara Rao et al 2022 ECS Trans. 107 1441 DOI 10.1149/10701.1441ecst … , 2022
    2022
    Citations: 4
  • BI HISTOGRAM EQUALIZATION BASED IMAGE ENHANCEMENT WITH BICUBIC INTERPOLATION
    B rao Jana, MAS Kumar, KVG Srinivas
    SGS-Engineering & Sciences 1 (01) , 2021
    2021
  • A safe and cost-effective algorithm for automation of LPG cylinder booking using ESP8266
    SN Nalla, KV Gowreesrinivas
    Microelectronics, Electromagnetics and Telecommunications: Proceedings of … , 2020
    2020
  • Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba Algorithm
    KV Gowreesrinivas, P Samundiswary
    Microelectronics, Electromagnetics and Telecommunications: Proceedings of … , 2020
    2020
  • High speed multipliers using counters based on symmetric stacking
    D KavyaShree, P Samundiswary, KV Gowreesrinivas
    2019 International Conference on Computer Communication and Informatics … , 2019
    2019
    Citations: 7
  • Resource efficient single precision floating point multiplier using Karatsuba algorithm
    VK Gowreesrinivas, P Samundiswary
    Indonesian Journal of Electrical Engineering and Informatics (IJEEI) 6 (3 … , 2018
    2018
    Citations: 3
  • Implementation and Analysis of Single Precision Floating Point Multiplication Using Vedic and Canonic Signed Digit Algorithm
    KV Gowreesrinivas, P Samundiswary
    2018 9th International Conference on Computing, Communication and Networking … , 2018
    2018
    Citations: 1
  • Design and Analysis of Single Precision Floating Point Multiplication with Vedic Mathematics Using Different Techniques
    KV Gowreesrinivas, P Samundiswary
    Microelectronics, Electromagnetics and Telecommunications: Proceedings of … , 2018
    2018
  • Power analysis of single precision floating point multiplication using Vedic with proposed techniques
    PS K V Gowreesrinivas
    International Journal of Engineering & Technology 7 (3.29), 443-446 , 2018
    2018
  • FPGA implementation of single-precision floating point multiplication with Karatsuba algorithm using vedic mathematics
    KV Gowreesrinivas, P Samundiswary
    Smart Computing and Informatics: Proceedings of the First International … , 2017
    2017
    Citations: 4
  • Comparative performance analysis of multiplexer based single precision floating point multipliers
    KV Gowreesrinivas, P Samundiswary
    2017 International conference of Electronics, Communication and Aerospace … , 2017
    2017
    Citations: 8
  • Comparative analysis of single precision floating point multiplication using compressor techniques
    KV Gowreesrinivas, P Samundiswary
    2017 International Conference on Wireless Communications, Signal Processing … , 2017
    2017
    Citations: 8

MOST CITED SCHOLAR PUBLICATIONS

  • Comparative study on performance of single precision floating point multiplier using vedic multiplier and different types of adders
    KV Gowreesrinivas, P Samundiswary
    2016 International Conference on Control, Instrumentation, Communication and … , 2016
    2016
    Citations: 13
  • FPGA implementation of a resource efficient vedic multiplier using SPST adders
    KV Gowreesrinivas, S Srinivas, P Samundiswary
    Engineering, Technology & Applied Science Research 13 (3), 10698-10702 , 2023
    2023
    Citations: 12
  • Comparative performance analysis of multiplexer based single precision floating point multipliers
    KV Gowreesrinivas, P Samundiswary
    2017 International conference of Electronics, Communication and Aerospace … , 2017
    2017
    Citations: 8
  • Comparative analysis of single precision floating point multiplication using compressor techniques
    KV Gowreesrinivas, P Samundiswary
    2017 International Conference on Wireless Communications, Signal Processing … , 2017
    2017
    Citations: 8
  • High speed multipliers using counters based on symmetric stacking
    D KavyaShree, P Samundiswary, KV Gowreesrinivas
    2019 International Conference on Computer Communication and Informatics … , 2019
    2019
    Citations: 7
  • Design and analysis of single precision floating point multiplication using Karatsuba algorithm and parallel prefix adders
    KV Gowreesrinivas, P Samundiswary
    2017 Fourth International Conference on Signal Processing, Communication and … , 2017
    2017
    Citations: 7
  • Fpga implementation of area efficient 16-bit vedic multiplier using higher order compressors
    P Sairam, K Manikumar, YS Reddy, BU Narayana, KV Gowreesrinivas
    2023 IEEE Devices for Integrated Circuit (DevIC), 404-407 , 2023
    2023
    Citations: 6
  • Design and analysis of turbo encoder using Xilinx ISE
    PP Kumar, KV Gowreesrinivas, P Samundiswary
    2016 International Conference on Control, Instrumentation, Communication and … , 2016
    2016
    Citations: 5
  • BI Histogram Equalization Based Image Enhancement with Bicubic Interpolation
    BSJ J Bhaskara Raoa*, K V G Srinivasb, A Siva Kumarc
    Jana Bhaskara Rao et al 2022 ECS Trans. 107 1441 DOI 10.1149/10701.1441ecst … , 2022
    2022
    Citations: 4
  • FPGA implementation of single-precision floating point multiplication with Karatsuba algorithm using vedic mathematics
    KV Gowreesrinivas, P Samundiswary
    Smart Computing and Informatics: Proceedings of the First International … , 2017
    2017
    Citations: 4
  • Design and implementation of hybrid full adder based 16-bit multiplication using FPGA
    KV Gowreesrinivas, BU Sri, S Saideepak, G Tarun, IS Sagar
    2023 IEEE Devices for Integrated Circuit (DevIC), 451-454 , 2023
    2023
    Citations: 3
  • Improvised hierarchy of floating point multiplication using 5: 3 compressor
    KV Gowreesrinivas, S P
    International Journal of Electronics Letters 10 (1), 87-100 , 2022
    2022
    Citations: 3
  • Resource efficient single precision floating point multiplier using Karatsuba algorithm
    VK Gowreesrinivas, P Samundiswary
    Indonesian Journal of Electrical Engineering and Informatics (IJEEI) 6 (3 … , 2018
    2018
    Citations: 3
  • Design And Implementation Of Power Efficient Multiplier Using Reversible Logic
    K Yashoda, KV Gowreesrinivas, MU Mahesh, KS Phanindra, A Syed, ...
    2025 Devices for Integrated Circuit (DevIC), 390-395 , 2025
    2025
    Citations: 2
  • High Speed Single Precision Floating Point Multiplier Using Vedic Multiplier and Knowles Adder
    KV Gowreesrinivas, P Samundiswary
    Proceedings of International Conference on Advanced Computing and … , 2017
    2017
    Citations: 2
  • Implementation and Analysis of Single Precision Floating Point Multiplication Using Vedic and Canonic Signed Digit Algorithm
    KV Gowreesrinivas, P Samundiswary
    2018 9th International Conference on Computing, Communication and Networking … , 2018
    2018
    Citations: 1
  • Design And Evaluation Of Energy-Efficient Approximate Multipliers
    PDP K V Gowreesrinivas , Ganesh Laveti, Chukka.Anoosha, Eswara Chaitanya ...
    International Journal of Environmental Sciences 11 (No. 16s), 2079-2089. , 2025
    2025
  • Optimizing Power Consumption: CSD-Based 16-Bit Multiplier for Low-Power Systems
    KV Gowreesrinivas, S Rahul, K Arjun, B Sushma, CM Sai
    2025 Devices for Integrated Circuit (DevIC), 407-411 , 2025
    2025
  • Performance Optimized 32-bit Multiplier: Integrating Vedic and Karatsuba Techniques
    KV Gowreesrinivas, B Vennela, L Sasank, AS Raghav, ...
    2025 Devices for Integrated Circuit (DevIC), 132-137 , 2025
    2025
  • BI HISTOGRAM EQUALIZATION BASED IMAGE ENHANCEMENT WITH BICUBIC INTERPOLATION
    B rao Jana, MAS Kumar, KVG Srinivas
    SGS-Engineering & Sciences 1 (01) , 2021
    2021