Borrow Save Adder Implementation Under Threshold Voltage Variability C. Kalamani, M. Jeba Paulin, P. Pattunnarajam, B. Paulchamy International Journal of Computational and Experimental Science and Engineering, 2025 It is commonly recognized that lower logic depth enables low voltage operation, which lowers power dissipation. But these circuits are especially prone to fluctuations, which could undermine the anticipated advantages. These short addresses the problem of increased threshold voltage variance by providing a low-power addition method that works under variability. In particular, by quantitatively comparing the effects of variation on the performances of ripple-carry adders (RCA) and borrow-save adders (BSA), the average power reduction that BSA achieves at low voltage values at the expense of increased delay variation is measured. This leads to a suggestion of a method that improves the performance of both adders. The calculated average power dissipation and maximum critical path delay variation of BSA at various supply voltages. It is demonstrated that a significant reduction in supply voltage is achievable, resulting reduction in BSA's overall power dissipation when compared to a counterpart operating at nominal voltage and maintaining a maximum delay lower than that of RCA. Moreover, straightforward design modifications that exchange latency for variability are incorporated in the BSA design, thereby lowering the maximum delay's normalized standard deviation.
Energy efficient Wallace multiplier using symmetric stacking counter circuit Kalamani C, Krishnammal V P, Balaji V R, Marimuthu C N Measurement Sensors, 2024 Multipliers show a dynamic part in numerous uses such as digital signal processing, filters and so on. Hence, the performance of the multiplier circuit has also to be improved more for better results. The circuit of the multiplier should be more compact and efficient to achieve the best outcome. Symmetric stacking counter circuit is designed using reversible logic gates and it reduces the power consumption. Various symmetric stacked counters are designed and used to implement the Wallace tree multiplier. The proposed multiplier is consumes 0.798mw of power and PDP of 2.47. The designed multiplier is power efficient as compared with existing methods with slight increase in delay. The proposed multiplier is used in low power application like modulators and demodulators.
Design of encoder and decoder using reversible logic gates C. Kalamani, R. Murugasami, S. Usha, S. Saravanakumar Measurement Sensors, 2024 The digital modules are the building block of all the applications in digital world. Encoders and decoders play a vital role in numerous applications. The Encoder - Decoder framework is a major stream deep learning design for all computing applications. The "encoder" uses a deep convolutional network to encode hierarchical data into feature maps, whereas the "decoder" uses encoded features to create efficient dense forecasts. The Encoder - Decoder platform's core principle is to understand data first and then forecast segmentation depending on the interpretation of the data. Reversible gates are the blooming technique now a day as they are really useful in reducing the power consumption.When the components are implemented using these gates it gives the optimized result. By analyzing the working of encoders and decoders, 8x3 encoder and decoder, hamming encoder, decoder are proposed using reversible gates. Their functionality is verified and power is obtained using Xilinx and Cadence tools. The proposed method of encoder and decoder show improvement, when compared with the existing designs.
An efficient reconfigurable FIR filter design with coefficient optimization using a modified bacterial foraging optimization algorithm C. Kalamani, S. Lekashri, A.N. Duraivel, T. Selvin Retna Raj Automatika, 2024 The digital filters play a significant role in the field of digital signal processing (DSP). The finite impulse response (FIR) filter is an attractive choice because of the ease of design and good stability. The digital filters have a wide variety of applications such as signal processing, control systems, telecommunication, etc. They are better than the analogue filters due to their performance. In recent times, software radios have achieved attention owing to requirements for integrated and reconfigurable communication systems. Hence, reconfigurations have emerged as a significant problem in the designs of FIRs. To match the frequencies of DSP applications, higher-order FIRs are required. If length of filters rises, addition and multiplication operations also increase. This paper proposes an efficient hardware design of RFIR that employs modified bacterial foraging optimizations (MBFOs) and common sub-expression eliminations (CSEs) in its executions. MBFOs output restricted counts of filter coefficients with sums of signed-power-of-two (SPT) terms while maintaining the quality of filtered responses. On obtaining coefficients, eliminations are executed by CSEs where hardware complexities are determined in terms of adders. Model sim software validated RFIRs using the Verilog code. The proposed design of RFIRs was compared with existing designs in terms of power usages, frequencies and areas.
Photographic Attendance Tracking System Online (PATSO) Rajadurai S, Dhinesh N, Karthikeyan S, Kalamani C Vitecon 2023 2nd IEEE International Conference on Vision Towards Emerging Trends in Communication and Networking Technologies Proceedings, 2023 Attendance tracking is critical to monitoring student or employee attendance in academic and organizational settings. With the rise of online education and remote work, traditional attendance tracking methods are becoming less effective. This paper proposes a web application for an image- based online attendance tracking system (PATSO) that utilizes machine learning algorithm SVM for classification and face recognition technique to identify and track attendance. The system gets a group or an individual image of students from the user and compares them to a pre-stored database of images to verify attendance. The proposed method is convenient, and accurate, and eliminates the need for manual attendance tracking not only in online mode but also in offline modes. The system's effectiveness was evaluated through a series of experiments, which showed a high accuracy rate of over 90%.
The design and implementation of folded adaptive lattice filter structures in FPGA for ECG signals Kalamani C., Kamatchi S., Sasikala S., Murali L. Automatika, 2023 An adaptive filter is the utmost essential filter castoff in statistical signal dealing. The fine-tuning of the filter factor in relation to the response signal is the adaptive filter's key feature due to fewer calculations, Least Mean Square (LMS) adaptive filters are widely used to remove noise from Electrocardiograms (ECG). The adaptive filters are realized as signal processing algorithms in Digital Signal Processors (DSPs) or in VLSI Signal Processors (VSPs). The technique provides a way to create a folded adaptive lattice LMS filter, which requires less hardware than an adaptive lattice filter. Folding is an algorithm that uses a time scheduling technique that combines arithmetic operations into one operation which reduces Register and silicon chip areas. The design and implementation of a folded lattice adaptive filter remove Power Line Interference (PLI) noise from ECG signals. The MATLAB Xilinx System Generator tool is used to design the Adaptive Lattice LMS Filter and Folded Adaptive Lattice LMS Filter with Folding Order K = 2 and K = 4 and realized in the Virtex 5 FPGA KIT. The results of the folded architecture show that the area is reduced for K = 2 and K = 4 by 82.60% and 91.05%, respectively compared with a normal adaptive lattice filter.
Design and Simulation of Microstrip Patch Antenna Using Circular Structure Kalamani. C, Abiramasundari. S, Dhanasekar. J, Ishwarya Niranjana. M 2023 9th International Conference on Advanced Computing and Communication Systems Icaccs 2023, 2023 Microstrip patch antennas are castoff in various applications. It uses resonant cavity for its radiation. The various antennas are designed in the past. The proposed antennas are designed with single patch, array with rectangular structure and array antenna with circular structure using ADS software. Both single and array with rectangular are operating in three band of frequency at 4.5,5. 7and 7.6 Giga hertz. The performances of these antennas are increased by inserting λ/4 between transmission line and patch. The performances improve further by making circular structure. This circular structure is operating in the 5.8 Gigahertz and used in RFID and WLAN application.
Design of Power and Delay Efficient Fault Tolerant Adder Kalamani C, Vivek Karthick Perumal, M. Vivek Kumar, J. Muralidharan Proceedings of the 3rd International Conference on Artificial Intelligence and Smart Energy Icais 2023, 2023 A power, delay efficient error acquiescent adder is proposed. In recent VLSI expertise, the manifestation of all categories of faults has developed foreseeable. By embracing an emergent perception in VLSI strategy, fault-tolerant adder (FTA) is suggested. The FTA is talented to comfort the harsh constraint on exactitude, and at the identical period accomplish marvelous enhancements in together the power ingestion and speediness enactment. For any transportable uses anywhere the power ingestion and speed are the utmost significant limit, one must diminish the power feeding and upsurge the speed as ample as probable. In this technique certain amendments are suggested to predictable adders to significantly decrease its power feeding. The amendments to the conservative building comprise the elimination of carry generation from LSB to MSB. With this the adder works at high speed with low power consumption.
Design of Power Delay Efficient Wallace Muliplier Kalamani. C, Dharani, Vanjipriya, Ishwarya Niranjana. M 2023 9th International Conference on Advanced Computing and Communication Systems Icaccs 2023, 2023 In applications involving image processing, multipliers are crucial. Area, potency, and delay analysis of the circuit are a few of the different metrics used to describe the performance of digital analysis. The 4-bit AXB is multiplied by a 4X4 Wallace tree resulting in the formation of a fractional creation, which causes an incrimination in latency. The delay is further decremented by inserting a 4-2 compressor in the fractional creation generation phase and it is used to implement 8bit Wallace multiplier to reduce delay. The simulated result shows a decrease in power and delay.
Automatic Head Gesture Controlled Robot Kalamani C, Pradeesh Kumar S, Kowsalya V, Vinith Rahul M 2022 International Conference on Communication Computing and Internet of Things Ic3iot 2022 Proceedings, 2022
Hybrid encoding for test data compression C. Kalamani, M. Mayilsamy, V. Rukkumani, K. Srinivasan, R. Mohan Kumar, K. Paramasivam Microprocessors and Microsystems, 2020
A mixed selected selective huffman coding and run length coding techniques for test data compression International Journal of Applied Engineering Research, 2014
RECENT SCHOLAR PUBLICATIONS
Minimized Multiplication Complexity for Image Processing Application by Using Serial Multiplier with Massive Volume of Data C Kalamani, B Radha, S Lekashri, M Ravishankar SN Computer Science 7 (5), 450 , 2026 2026
Enhancing information security and fault coverage in BIST with non-linear register updation KASC Kalamani Chinnappa Gounder, Mythrayee D Information Security Journal: A Global Perspective 35 (1), 237-250 , 2025 2025
An improved distance vector hop algorithm and A* algorithm with modified supernova optimizer for 3-dimensional localization in wireless sensor networks K Muthusamy, Sudha , Ruby, Erode Dhanapal Kanmani, Arunachalam, Rajesh ... Wireless Networks , 2025 2025 Citations: 5
Borrow Save Adder Implementation Under Threshold Voltage Variability BP C. Kalamani, M.Jeba Paulin, P.Pattunnarajam International Journal of Computational and Experimental Science and … , 2025 2025
Energy efficient Wallace multiplier using symmetric stacking counter circuit C Kalamani, VP Krishnammal, VR Balaji, CN Marimuthu Measurement: Sensors 35, 101267 , 2024 2024 Citations: 15
Animal and Violence Detection Using Artificial Neural Network RS Kalamani C, Bhuvaneswaran R, Dhanapal S IJMER 13 (4), 168-178 , 2024 2024
Design of encoder and decoder using reversible logic gates C Kalamani, R Murugasami, S Usha, S Saravanakumar Measurement: Sensors 31, 100989 , 2024 2024 Citations: 21
An efficient reconfigurable FIR filter design with coefficient optimization using a modified bacterial foraging optimization algorithm C Kalamani, S Lekashri, AN Duraivel, T Selvin Retna Raj Automatika: časopis za automatiku, mjerenje, elektroniku, računarstvo i … , 2024 2024 Citations: 17
The design and implementation of folded adaptive lattice filter structures in FPGA for ECG signals C Kalamani, S Kamatchi, S Sasikala, L Murali Automatika: časopis za automatiku, mjerenje, elektroniku, računarstvo i … , 2023 2023 Citations: 17
ASIC Flash Analog to Digital Convertor Using Operational Amplifier RPV C.Kalamani , Ram Karthik Kumar K., Kalai Selvi B. Tuijin Jishu\journal of Propulsion Technology 44 (6), 2437-2444 , 2023 2023
Design and Simulation of Microstrip Patch Antenna Using Circular Structure Kalamani.C, Abiramasundari.S,Dhanasekar.j 2023 9th International Conference on Advanced Computing and Communication … , 2023 2023
Design of Power Delay Efficient Wallace Muliplier NM Kalamani.C, Dharani, Vanjipriya 2023 9th International Conference on Advanced Computing and Communication … , 2023 2023
IoT based Smart Intravenous Fluids (IV) Drip Monitoring and Reverse Blood Flow Prevention System V Kumar M, R Sundar. G, M K, K C, S S IEEE-2023 International Conference on Intelligent Data Communication … , 2023 2023
Design of power and delay efficient fault tolerant adder C Kalamani, VK Perumal, MV Kumar, J Muralidharan 2023 Third International Conference on Artificial Intelligence and Smart … , 2023 2023 Citations: 14
ACCIDENT PREVENTION IN HILLY AREAS BY ALERT SYSTEM C Kalamani JOURNAL OF ENGINEERING, COMPUTING & ARCHITECTURE 12 (6), 190-197 , 2022 2022
HAND GESTURE CONTROLLED CAR Dr.Kalamani C, Saamsundar K V , Mithun Adthiya P V JOURNAL OF ENGINEERING, COMPUTING & ARCHITECTURE 12 (6), 112-120 , 2022 2022
Automatic Head Gesture Controlled Robot K C, P Kumar S, K V, V Rahul M IEEE-2022 International Conference on Communication, Computing and Internet … , 2022 2022
DESIGN OF ADIABATIC CIRCUITS WITH REVERSIBLE LOGIC BASED FULL ADDER AND MULTIPLIER IN CURRENT-MODE LOGIC CIRCUITS FOR EFFICIENT POWER DISSIPATION, C. Kalamani, V.S. Nishok, A. Asha, S. Saravanakumar Optik,, 170438, , 2022 2022 Citations: 15
IMPLEMENTATION OF KEYLESS DOORLOCK SYSTEM USING RASPERRY PI AND MOBILE APPLICATION Kalamani C, Shafiudeen M, Lakshmi Prabha V, Uva Priya V.G Vidyabharati International Interdisciplinary Research Journal ISSN: 2319 … , 2021 2021
Design and Development of Human Safety Detection Using GPS, GSM and RFID Technology Dr.Kalamani C, Athi Lakshmi G, Akshaya S Contemporary researCh in engineering and management 2, 31-44 , 2021 2021
MOST CITED SCHOLAR PUBLICATIONS
Design of Differential LNA and Double Balanced Mixer using 180 nm CMOS Technology C Kalamani Microprocessors and Microsystems 71 (1), - , 2019 2019 Citations: 28
Design of encoder and decoder using reversible logic gates C Kalamani, R Murugasami, S Usha, S Saravanakumar Measurement: Sensors 31, 100989 , 2024 2024 Citations: 21
An efficient reconfigurable FIR filter design with coefficient optimization using a modified bacterial foraging optimization algorithm C Kalamani, S Lekashri, AN Duraivel, T Selvin Retna Raj Automatika: časopis za automatiku, mjerenje, elektroniku, računarstvo i … , 2024 2024 Citations: 17
The design and implementation of folded adaptive lattice filter structures in FPGA for ECG signals C Kalamani, S Kamatchi, S Sasikala, L Murali Automatika: časopis za automatiku, mjerenje, elektroniku, računarstvo i … , 2023 2023 Citations: 17
Hybrid encoding for test data compression C Kalamani, M Mayilsamy, V Rukkumani, K Srinivasan, RM Kumar, ... Microprocessors and Microsystems 77, 103169 , 2020 2020 Citations: 16
Design and Implementation of 4 Bit Multiplier Using Fault Tolerant Hybrid Full Adder C Kalamani, VA Karthick, S Anitha, KK Kumar International Journal of Electrical, Electronic and Communication Sciences … , 2017 2017 Citations: 16
Energy efficient Wallace multiplier using symmetric stacking counter circuit C Kalamani, VP Krishnammal, VR Balaji, CN Marimuthu Measurement: Sensors 35, 101267 , 2024 2024 Citations: 15
DESIGN OF ADIABATIC CIRCUITS WITH REVERSIBLE LOGIC BASED FULL ADDER AND MULTIPLIER IN CURRENT-MODE LOGIC CIRCUITS FOR EFFICIENT POWER DISSIPATION, C. Kalamani, V.S. Nishok, A. Asha, S. Saravanakumar Optik,, 170438, , 2022 2022 Citations: 15
Survey of Low Power Testing Using Compression Techniques C Kalamani, DK Paramasivam International Journal of Electronics & Communication Technology 4 (4), 13-18 , 2013 2013 Citations: 15
Design of power and delay efficient fault tolerant adder C Kalamani, VK Perumal, MV Kumar, J Muralidharan 2023 Third International Conference on Artificial Intelligence and Smart … , 2023 2023 Citations: 14
A combined compatible block coding and run length coding techniques for test data compression C Kalamani, K Paramasivam World Applied Sciences Journal 32 (11), 2229-2233 , 2014 2014 Citations: 13
A Modified Run Length Coding Technique for Test Data Compression Based on Multi-Level Selective Huffman Coding C Kalamani International Journal of Electronics and Communication Engineering 11 (1 … , 2017 2017 Citations: 11
Test Data Compression using a hybrid of bitmask dictionary and 2n Pattern Runlength Coding Methods C Kalamani, K Paramasivam World Academy of Science, Engineering and Technology 9 (3), 1289-1294 , 2015 2015 Citations: 11
An improved distance vector hop algorithm and A* algorithm with modified supernova optimizer for 3-dimensional localization in wireless sensor networks K Muthusamy, Sudha , Ruby, Erode Dhanapal Kanmani, Arunachalam, Rajesh ... Wireless Networks , 2025 2025 Citations: 5
Minimized Multiplication Complexity for Image Processing Application by Using Serial Multiplier with Massive Volume of Data C Kalamani, B Radha, S Lekashri, M Ravishankar SN Computer Science 7 (5), 450 , 2026 2026
Enhancing information security and fault coverage in BIST with non-linear register updation KASC Kalamani Chinnappa Gounder, Mythrayee D Information Security Journal: A Global Perspective 35 (1), 237-250 , 2025 2025
Borrow Save Adder Implementation Under Threshold Voltage Variability BP C. Kalamani, M.Jeba Paulin, P.Pattunnarajam International Journal of Computational and Experimental Science and … , 2025 2025
Animal and Violence Detection Using Artificial Neural Network RS Kalamani C, Bhuvaneswaran R, Dhanapal S IJMER 13 (4), 168-178 , 2024 2024
ASIC Flash Analog to Digital Convertor Using Operational Amplifier RPV C.Kalamani , Ram Karthik Kumar K., Kalai Selvi B. Tuijin Jishu\journal of Propulsion Technology 44 (6), 2437-2444 , 2023 2023
Design and Simulation of Microstrip Patch Antenna Using Circular Structure Kalamani.C, Abiramasundari.S,Dhanasekar.j 2023 9th International Conference on Advanced Computing and Communication … , 2023 2023
