BHASKAR GUGULOTHU
@osmania.ac.in
Scopus Publications
Scholar Citations
Scholar h-index
Scopus Publications
Mallikarjun Vasam, Balaji Maddiboyina, Chandrashekar Talluri, Shanmugarathinam Alagarsamy, Bhaskar Gugulothu, and Harekrishna Roy
Springer Science and Business Media LLC
Bhaskar Gugulothu and Rajendra Naik Bhukya
Springer Science and Business Media LLC
Bhaskar Gugulothu and B.Rajendra Naik
IEEE
In this paper, the crosstalks induced effects are explored in mutually coupled multi-walled carbon nanotubes (MWCNTs) interconnect lines driven by CMOS gates. The crosstalk delays and the peak voltages on the victim line for functional and dynamic crosstalk are investigated. The analyzes has been done for multiwalled carbon nanotubes and copper on-chip interconnects for 22nm technology node. The results show that exploiting the MWCNT interconnects instead of Cu leads to 61.35% shorter functional crosstalk delay, 12.80% lower functional crosstalk voltage and 59.14% lower dynamic in-phase crosstalk delay and 67.38% lower dynamic out-phase crosstalk delay. For different load capacitances utilizing the MWCNT interconnects instead of Cu leads to 62.79% shorter functional crosstalk delay, 63.54% lower dynamic in-phase crosstalk delay and 68.24% lower dynamic out-phase crosstalk delay. The simulation results show that the MWCNT is significantly highly efficient than conventional copper (Cu) on-chip interconnects. It is observed the results shows that the MWCNT are more fit for very large-scale integration system as compared to the Cu.
Bhaskar Gugulothu and Rajendra Naik Bhukya
The Electrochemical Society
Raju Mudavath, B. Rajendra Naik, and Bhaskar Gugulothu
IEEE
In high-speed regime, as the PCBs (Printed Circuit Boards) are diminished, and the continuous increasing of the clock frequency in the state-of-the-art digital systems, at higher frequencies there is no more interconnects are transparent. The behavior of the electrical properties of traces (Transmission lines) plays a major role in determining the performance of the PCB board. As an enormous increase of frequencies and usage of data rates and decreasing of size, it's necessary to check the signal integrity issues on a PCBs to reduce failure products. In this paper, we design and analyzed the coupled transmission lines for a single-ended micro-strip model with $50\\Omega$ characteristic impedance and extracted RLC parameters. Estimated the Near End Crosstalk(NEXT) and Far End Crosstalk (FEXT) noise in ADS and validated with SPICE Tool on victim line and also, compared with an empirical equations values.
Bhaskar Gugulothu, B. Rajendra Naik, and Sampath Boodidha
IEEE
In this paper, we estimated the crosstalk noise for CMOS driver with capacitive coupled interconnect model in High-speed digital VLSI circuits. Crosstalk noise is one of the essential parameters for designing accurate interconnect models. As monotonically increasing of clock frequencies, circuit density and decreasing of rise time, degrading the circuit performance. The design of L - Model Interconnect with capacitively coupled at high frequencies, estimated the crosstalk noise on victim lines on both ends with respect to aggressor line for global interconnects at 180nm Technology Node. And also carried out the analytical and simulated results in Advanced Design System (ADS) and validated with SPICE tool.