Dr. Shyam Akashe is a professor in Electronics & Communication Engineering Department and Dean International Cooperation & Projects at ITM University Gwalior. He received M.Tech degree in Electronics & Communication Engineering from Rajiv Gandhi Proudyogiki Vishwavidyalaya (RGPV), Bhopal in 2006 and Ph.D. Thapar University, Patiala (previously Thapar Institute of Engineering and Technology), Punjab in 2013. During his Ph. D. studies, he worked on Low power memory cell design.
After joining ITM University Gwalior in 2012, he leads as an M.Tech VLSI Design coordinator, focusing on low power VLSI design, modeling, FinFET based memory design, circuits for future VLSI technology, digital design and FPGA implementation. This has resulted in over 300 peer-reviewed journal and conference papers and holds more than 10 patents.
Dr. Akashe received the NSC-2005 at IIT Bombay best research paper award and his Biographical profile published in Marquis’s Who’s Who in Engineering Field, USA awarded b
EDUCATION
Ph.D. in Electronics & Communication Eng. Thapar University, Patiala, Punjab, India, 2013.
M.Tech. in Electronics & Communication Eng. Institute of Technology & Management, Gwalior, (M.P.), India, 2006.
Energy-Efficient Neuromorphic Architectures Enabled by Resistive Memory Joshika Sharma, Shyam Akashe Journal of Trends in Computer Science and Smart Technology, 2025 Their excellent performance and compatibility with CMOS technology, while the OXRAM (Oxide-based CMOS Resistive Random Access Memory) technique used in CMOS transistors presents challenges in terms of device unpredictability and scalability, also offers potential advantages such as higher endurance, lower power consumption, and quicker reading and writing operation speeds when compared to traditional Flash memory. The inability of conventional SRAMs to store data after powering off limits their use in battery-operated mobile devices and other applications where non-volatility related to zero leakage currents is required. In the article, a new OXRAM-based Non-Volatile SRAM (NVSRAM) device is presented. It is suggested to compare the performance of SRAM with NVSRAM at the memory and cell levels. Learning is crucial for the brain's ability to adapt to changing conditions. A synaptic connection table in an external memory at a local routing node is used to learn a rule in the address domain for neuromorphic architecture. A number of parameters are compared, including design complexity, leakage current values (SRAM cells are 3.4µA, 7.4nA) and (NVSRAM-based OXRAM are 2.7 µA, 5.9nA) at 180nm and 90nm, and energy saving or power usage values (SRAM cells cell are 5.5 µA, 10.5nA) and (NVSRAM based OXRAM are 4.9 µA, 9.8nA) at 180nm and 90nm. The circuits that are being described can be realized using far-above ground voltage CMOS Cadence tools at 180 nm and 90 nm.
