Jeetendra Singh
@nitsikkim.ac.in
Assistant Professor, Electronics and Communication Engineering
NIT Sikkim
EDUCATION
Ph.D. (VLSI DESIGN)
Dr. B R Ambedkar NIT Jalandhar, Jalandhar
Title: Modeling and Simulation of Memristor for Memory Cell Design
Awarded (November 25, 2019)
M.Tech (Microwave Electronics)
University of Delhi, New Delhi
Project: Design and Development of C Band RF Down-Converter
D.E.A.L. (DRDO) DEHRADUN
1st Div., 2012
B.Tech (Electronics & Communication Engg.)
Uttar Pradesh Technical University, Lucknow
1st Div., 2009
GATE Qualified (2022)
RESEARCH INTERESTS
Physical modeling, simulations, fabrications, electrical characterizations of semiconductor devices and their implementation in the designing of high speed, low power mixed-signal (digital/analog) circuits in the regime of submicron technology of CMOS.
Scopus Publications
Scopus Publications
Shailendra Singh and Jeetendra Singh
Springer Science and Business Media LLC
Girish Wadhwa, Jeetendra Singh, Anchal Thakur, and Sheetal Bhandari
Elsevier BV
Shailendra Singh and Jeetendra Singh
World Scientific Pub Co Pte Ltd
In this paper, a negative capacitance (NC) effect in series with normal oxide capacitance is first time introduced to design negative capacitance charge plasma-based junction less vertical TFET structure (NC-CP-JL-VTFET). The introduced negative capacitance enhances the overall gate capacitance and hence gate capacitive coupling and thus renders high current capabilities with reduced sub-threshold slope and threshold voltage. With the use of negative capacitance along with oxide capacitance, it has been seen that the same drain current is achieved at lower gate voltage as compared to without use of negative capacitance and since the voltage scaling is done considerably, the dynamic power dissipation in circuit application can be reduced significantly. To generate the negative capacitance during the device operation; ferroelectric material [Formula: see text](VDF-TrFE) poly(vinylidene fluoride-trifluoro ethylene) is used in stack with SiO2 gate oxide. Various performance parameters of the designed structure such as electron–hole concentration in the tunneling junction, electric field, surface potential, electron–hole quasi-Fermi variation, and drain current variation are investigated and compared with the results of without considering the ferroelectric material in the gate oxide. The variation of the ferroelectric thickness on the device performance is also investigated. The investigation exhibits significant improvement in the drain current and in the other parameters as well. These improvements are seen because of higher capacitive coupling and these effects are further responsible for more energy band bending which in turn govern high electron tunneling. Due to the existence of negative capacitance, the peak value of the electric field gets doubled while the surface potential increases 44% from the normal structure.
Susheel Kumar Singh, Mukesh Kumar, and Jeetendra Singh
Springer Science and Business Media LLC
Jeetendra Singh, Girish Wadhwa, and Balwinder Raj
Springer Science and Business Media LLC
Shailendra Singh, Raghav Dwivedi, Jeetendra Singh, and Balwinder Raj
Elsevier
Jeetendra Singh, Shailendra Singh, and Neha Paras
Springer Science and Business Media LLC
Shailendra Singh, Jeetendra Singh, Arun Kumar Singh, and Manoj Kumar Shukla
Springer Science and Business Media LLC
Chhaya Verma, Jeetendra Singh, Santosh Kumar Tripathi, and Rajeev Kumar
Springer Science and Business Media LLC
Jeetendra Singh, Archana Verma, Vijay Kumar Tewari, and Shailendra Singh
Springer Science and Business Media LLC
Shailendra Singh, Archana Verma, Jeetendra Singh, and Girish Wadhwa
Springer Science and Business Media LLC
Shailendra Singh, Amit Kumar Singh Chauhan, Gaurish Joshi, and Jeetendra Singh
Springer Science and Business Media LLC
Chhaya Verma and Jeetendra Singh
Springer Science and Business Media LLC
Jeetendra Singh and Chhaya Verma
Springer Science and Business Media LLC
Jeetendra Singh, Debapriya Chakraborty, and Naveen Kumar
Springer Science and Business Media LLC
Chhaya Verma and Jeetendra Singh
CRC Press
Jeetendra Singh, Sanjeev Kumar Sharma, and Balwinder Raj
Springer Science and Business Media LLC
Jeetendra Singh and Girish Wadhawa
Springer Science and Business Media LLC
Girish Wadhwa, Priyanka Kamboj, Jeetendra Singh, and Balwinder Raj
Springer Science and Business Media LLC
Girish Wadhwa, Jeetendra Singh, and Balwider Raj
Springer Science and Business Media LLC
Jeetendra Singh
Springer Science and Business Media LLC
Chhaya Verma and Jeetendra Singh
CRC Press
In 1971, the electrical resistance, the three key elements of the inductor and capacitor has been known. 1971 Reonchua Professor proposing theoretically requires significant electronics district «memristor». Memristor, the amplitude of the voltage applied on the resistor, two terminals depending on the direction and length of this element. This item, open a wide range of research and the potential application of memristor later, will take place in 2008 by HP Labs, Inc. In this article, machine, manufacturing, describes the characteristics of some of the possible future extension of the memristor approach. Also, in some applications, check the memory of the static digital and analog application and improvement of the future.
Debapriya Chakraborty, Jeetendra Singh, and Shashi Bala
IGI Global
This chapter encompasses the gradual requirements, basic working principle, inbuilt physics, structural and functional characteristics, and applications of nanowires, especially that of semiconductor nanowires in depth. Today, research and development in material science and electronics going hand in hand have opened up numerous directions for the exploration and utilization of several unique semiconducting materials in the design of novel field-effect-transistors (FETs) in the nano-scale architecture. The performance results of the basic NWFETs structures and hetero-structures along with methods to organize nanowires in the form of arrays to fulfill the requirement of integration of devices and circuits are described in detail. This chapter would be beneficial for students of undergraduate and postgraduate, researchers, and the industrial peoples as well who are working in the regime of the advancement of semiconductor technology because every aspect of nanowire and NWFETs is discussed here deeply in a single platform.
Shashi Bala, Raj Kumar, Jeetendra Singh, and Sanjeev Kumar Sharma
IGI Global
This chapter presents the design and simulation analysis nanowire-based FET (NWFET) for best possible Ig-Vgs characteristics. A NWFET is a device in which channel is wire-like structure with diameter or lateral dimension in nanometer (10-9 m) range. Performance analysis has been done for various design and process parameters variation to propose optimized parameter for best performance. Although a lot of focus has been put on homogenous Si based NWFETs, there has been a rising interest in III-V NWFETs. This is mainly due to the excellent carrier transport properties are provided by these materials. NWFETs have ability to suppress SCEs and are also good in suppressing OFF-current (IOFF), because of gate all around (GAA) configuration. Secondly, NWFETs have large ON-current (ION) due to quasi one-dimensional (1D) conduction of NWs, and as a result of low carrier scattering, conduction of NWs-based devices is very large.
Girish Wadhwa and Jeetendra Singh
Springer Science and Business Media LLC