Dr.R.Saravanan
@veltechmultitech.org
Professor Department of Computer Science and Engineering
VelTechMultiTech Dr.Rangarajan Dr.Sagunthala Engineering College
Scopus Publications
Scholar Citations
Scholar h-index
Scholar i10-index
Scopus Publications
R. Saravanan, S. Palanikumar, and M. Lenin Kumar
IEEE
Monitoring pregnancy woman health is continuos and vital process. Approximately 830 women die a day from pregnancy-related causes in India. In developing countries, still more number of maternal death is happening and the medical information is not centralized for sharing. In rural areas, there is a lack of adequate facilities to the pregnant women for their routine checkup and this ends up with a higher infant and maternal death rate. The resulting health issue is a challenge to rural community people. With the recent developments in the IoT based technology, pregnant women are continuously monitored through suitable sensors. The sensor data are streamed to the centralized server through wireless technology for monitoring and performing data analytics. The proposed work utilizes an acceleration wireless sensor to observe the live movement of the fetus, along with scanned ultrasound images. Other vital parameters including movement sign, pulse, pressure, SPO2, sleep, count the amount of kicks of the unborn baby, and measuring the ECG pattern of the pregnant women. The goal of the proposed work is to effectively monitor the health condition of pregnant woman through sensors and if any abnormality is being observed, it will send an early warning message to the medical professional. In the proposed architecture, a massive amount of unstructured sensor data is collected through microcontrollers and the data are streamed to Apache Kafka and stored in MongoDB. Results shows that, a complete pregnant woman monitoring system is developed and data analytics can be performed, which enable the medical professional and other recipient to monitor pregnant women's activities from anywhere at any time. In the case of emergency, an email / SMS notifications send to the doctor and other recipients.
R. Saravanan, V. Nehru, and S. Muthuselvi
IEEE
The population of the tribal people has been decreased day by day in India due to the lack of awareness in health related issues and there is a series challenges in their sustainable livelihood. The Particularly Vulnerable People from tribal groups (PVTGs) engaged in animal husbandry and poultry farming as their primary source of income, which improves their standard of living. Maintain and safeguard poultry and animals from diseases is a cumbersome process. Providing enough medical facility is still a challenging task due to the geographical location and unavailability of the infrastructure and human resources. The proposed framework uses Apache Kafka-Apache Storm-NoSQL Mongo DB architecture to process enormous volume of sensor data in real time and it receives the sensor data and uses it to create the various disease identification models. The processed data are stored in Mongo DB as a historical data. The system provides a Web-based monitoring system for continuos monitoring the health conditions of cattles and poultry through the Smart Health Care Centre. Smartness in operation is performed through System on Chip (SoC) IoT system, the proposed big data expert system model transcends from the traditional functionalities of disease identification by the real time field visit analysis by the medical professionals. The proposed system is more suitable for the remote hill area. Smart Health Care system improves the disease identification accuracy and provides a powerful Big Data architecture for data analytics and data storage. The big data expert system frame work is underwent successful functional testing of "SoC-IoT smart devices" connected with the network and the performance of the network in terms of CPU, memory usage and the network delay is analyzed. Further the frame work uses the big data processing with the machine learning approach "Hybrid diseases identification Model" with the combination of DBSCAN for outlier detection together with Random Forest classification, which improves the disease identification accuracy of the various disease attacked the cattles and poultry.
Arodh Lal Karn, Panneer Selvam Manickam, R. Saravanan, Roobaea Alroobaea, Jasem Almotiri, and Sudhakar Sengan
Computers, Materials and Continua (Tech Science Press)
Suresh Kumar V, Rajesh Khanna M, and Saravanan R
The Electrochemical Society
In this research paper, we discussed the guaranteed reliable communication between nodes by constructing the black hole attack free route in MANET. To achieve this, a Hybrid Intrusion Detection System (HIDS) technique has been proposed to detect and remove the black hole attack nodes in the routing path. In MANETs, a novel cluster leader election process has been proposed. This election process is based on the node with maximum energy level. One of the important functionality is security in MANET. Due to many different attacks in the routing path, MANET becomes unsecure. Understanding the form of attacks is always the main step towards the secured communication between mobile nodes. Routing protocols are significant to guarantee proper functioning of the path from source to destination nodes. This preserves the security of MANET from attacks.
Sushaptha Rajagopal, R. Vani, J. C. Kavitha, and R. Saravanan
Springer International Publishing
V. Balamurugan and R. Saravanan
Springer Science and Business Media LLC
Sivakami Raja and Saravanan Ramaiah
Springer Science and Business Media LLC
Sivakami Raja, Jaiganesh M., and Saravanan Ramaiah
Springer Science and Business Media LLC
V. Thirunavukkarasu, R. Saravanan, and V. Saminadan
IEEE
Universal Asynchronous Receiver Transmitter (UART) is used for exchanging data between computer and peripherals at a very short distance. In this paper, Built in Self Test (BIST) architecture with Bit Swapping Linear Feedback Shift Register (BS-LFSR) is used for testing UART. Generally, BIST for UART consists of test patterns obtained from conventional LFSR. BS-LFSR consists of shift registers, Multiplexers and a XOR logic gate. Pattern generation in BS-LFSR is similar to the normal LFSR but the sequence of the test pattern will be different. This method reduces the power consumption during testing of circuits by reducing number of switching activities when compared to the conventional LFSR. In the Bit-swapping LFSR maintaining randomness in the test pattern generation is the most important factor. Because of this randomness it gives high fault coverage. The main advantages of this work are better power reduction and less hardware requirement.
M. S Durairajan, R Saravanan, and S. Sibi Chakkaravarthy
American Scientific Publishers
Sivakami Raja and Saravanan Ramaiah
Springer Science and Business Media LLC
S. Pandiarajan, S. Senthil Kumaran, L.A. Kumaraswamidhas, and R. Saravanan
Elsevier BV
Sivakami Raja and Saravanan Ramaiah
Walter de Gruyter GmbH
Abstract Knowing the trust level of cloud service providers is a significant issue in the field of cloud computing for privacy and security reasons. The idea of this paper is to build up a Consumer and Cloud-Data Envelopment Analysis (CCDEA) trust assessment model for evaluating cloud services in two stages. In first stage, the believability index of each cloud Consumer (C) is calculated. The second stage incorporates Cloud-Data Envelopment Analysis (C-DEA) model for the trust assessment of cloud services from the viewpoint of cloud consumers. Several experiments were conducted and the results were analyzed to show the stability of our method in measuring the relative efficiency and effectiveness of cloud services through ranking mechanism.
Revathy
Science Publications
In this study, we propose a low power, high efficient Low Density Parity-Check Code (LDPC) Decoder Architecture for error detection and correction applications. LDPC codes have been adopted in latest wireless standards such as satellite and mobile communications since they possess superior error-detecting and correcting capabilities. As technology scales, memory devices become larger and more powerful and low power consumption based error correction codes are needed. This study discuses the design and analysis of check node unit and variable node unit in LDPC decoder. The architecture is synthesized on Xilinx 9.2i and simulated using Modelsim, which is targeted to 90 nm device. Synthesis report shows that the proposed architecture reduces the hardware utilization and power consumption when compared to the conventional architecture design.