Safaa sahib omran
@mtu.edu.iq
Middle technical university
Scopus Publications
Scholar Citations
Scholar h-index
Scholar i10-index
Scopus Publications
Mays K. Faeq and Safaa S. Omran
Institute of Advanced Engineering and Science
In modern techniques of building processors, manufactures using more than one processor in the integrated circuit (chip) and each processor called a core. The new chips of processors called a multi-core processor. This new design makes the processors to work simultanously for more than one job or all the cores working in parallel for the same job. All cores are similar in their design, and each core has its own cache memory, while all cores shares the same main memory. So if one core requestes a block of data from main memory to its cache, there should be a protocol to declare the situation of this block in the main memory and other cores.This is called the cache coherency or cache consistency of multi-core. In this paper a special circuit is designed using very high speed integrated circuit hardware description language (VHDL) coding and implemented using ISE Xilinx software. The protocol used in this design is the modified, exclusive, shared and invalid (MESI) protocol. Test results were taken by using test bench, and showed all the states of the protocol are working correctly.
Rusul Khalil Saad and Safaa S. Omran
Institute of Advanced Engineering and Science
Many systems like the control systems and in communication systems, there is usually a demand for matrix inversion solution. This solution requires many operations, which makes it not possible or very hard to meet the needs for real-time constraints. Methods were exists to solve this kind of problems, one of these methods by using the LU decomposition of matrix which is a good alternative to matrix inversion. The LU matrices are two matrices, the L matrix, which is a lower triangular matrix, and the U matrix, which is an upper triangular matrix. In this paper, a design of dual-core processor is used as the hardware of the work and certain software was written to enable the two cores of the dual-core processor to work simultaneously in computing the value of the L matrix and U matrix. The result of this work are compared with other works that using single-core processor, and the results found that the time required in the cores of the dual-core is more less than using single-core. The designed dual-core processor is invoked using the VHDL language.
Ali S. Al-Khalid and Safaa S. Omran
Institute of Advanced Engineering and Science
In the modern microprocessors that designed with pipeline stages, 
 the performance of these types of processors will be affected when executing branch instructions, because in this case there will be stalls in the pipeline. In turn this causes in reducing the Cycle Per Instruction (CPI) of the processor. In the case of executing a branch instruction, the processor needs an extra clocks to know if that branch will happen (Taken) or not (Not Taken) and also it requires calculating the new address in the case of the branch is Taken. The prediction that the branch is T / NT is an important stage in enhancing the processor performance. In this research more than one method of branch prediction (hybrid) is used and the designed circuit will choose different types of prediction algoritms depending on the type of the branch. Some of these methods were used are static while the other are dynamic. All circuits were built practically and examined by applying different programs on the designed predictor algorithm to compute the performance of the processor.
Safaa S. Omran, Ali Sh. Al-Khalid, and Amer Atta Yaseen
Institute of Advanced Engineering and Science
During recent years, nonlinear power electronic equipments introduce harmonic pollution on electric power systems. It makes the traditional power factor meter can not act accurately when it monitors unbalanced and harmonic loads. In this paper, a new algorithm for detecting the power factor in presence of non-sinusoidal load current is proposed. The proposed algorithm detects the true power factor exactly. By uses only two successive sampled data points of the voltage and the current for each displacement power factor value calculation and two sampled data points for each distortion power factor value calculation, the total/true power factor becomes easy to measure using these values directly. The proposed detector implemented using microcontroller as a main part and has been tested for single phase power system. The test results show that it can measure the true power factor of the loads quickly and accurately.
H S Mahmood and S S Omran
IOP Publishing
Safaa S. Omran and Aqeel A. Al-Hilali
IEEE
Safaa S. Omran and Ibrahim A. Amory
IEEE
Safaa S. Omran and Ahmed K. Abdul-abbas
IEEE
Safaa S. Omran and Ahmed K. Abdul-abbas
IEEE
Safaa S. Omran and Ahmed K. Abdul-abbas
IEEE
Safaa Sahib Omran and Laith Fouad Jumma
IOP Publishing
Safaa S. Omran and Ahmed K. Abdul-abbas
Science Publishing Corporation
Hardware design of multicore 32-bits processor is implemented to achieve low latency and high throughput QR decomposition (QRD) based on two algorithms which they are Gram Schmidt (GS) and Givens Rotation (GR). The orthogonal matrices are computed using the first core processor by Gram Schmidt algorithm, and the upper triangular matrices are computed using the second core processor by Givens Rotation algorithm. This design of multicore processor can achieve 50M QRD/s throughput for (4 × 4) matrices at running frequency 200 MHz.
Safaa S. Omran and Laith F. Jumma
IEEE
Safaa S. Omran and Jumana A. Jarallah
IEEE
Safaa S. Omran and Laith F. Jumma
IEEE
Safaa S. Omran and Jumana A. Jarallah
IEEE
Safaa S. Omran and Ibrahim A. Amory
IEEE
Safaa S. Omran and Ibrahim A. Amory
IEEE
Safaa S. Omran and Aqeel A. Al-Hillali
IEEE
Hadeel Sh. Mahmood and Safaa S. Omran
IEEE
Ali. Sh. Al-Khalid and Safaa. S. Omran
IEEE
S. S. Omran, A. S. Al-Khalid, and D. M. Al-Saady
IEEE
S S Omran, A S Al-Khalid, and D M Al-Saady
IEEE