Safaa sahib omran
@mtu.edu.iq
Middle technical university
14
Scopus Publications
131
Scholar Citations
4
Scholar h-index
3
Scholar i10-index
Scopus Publications
- Cache coherency controller for MESI protocol based on FPGA
Mays K. Faeq and Safaa S. Omran
Institute of Advanced Engineering and Science
In modern techniques of building processors, manufactures using more than one processor in the integrated circuit (chip) and each processor called a core. The new chips of processors called a multi-core processor. This new design makes the processors to work simultanously for more than one job or all the cores working in parallel for the same job. All cores are similar in their design, and each core has its own cache memory, while all cores shares the same main memory. So if one core requestes a block of data from main memory to its cache, there should be a protocol to declare the situation of this block in the main memory and other cores.This is called the cache coherency or cache consistency of multi-core. In this paper a special circuit is designed using very high speed integrated circuit hardware description language (VHDL) coding and implemented using ISE Xilinx software. The protocol used in this design is the modified, exclusive, shared and invalid (MESI) protocol. Test results were taken by using test bench, and showed all the states of the protocol are working correctly. - Design and implementation of dual-core MIPS processor for LU decomposition based on FPGA
Rusul Khalil Saad and Safaa S. Omran
Institute of Advanced Engineering and Science
Many systems like the control systems and in communication systems, there is usually a demand for matrix inversion solution. This solution requires many operations, which makes it not possible or very hard to meet the needs for real-time constraints. Methods were exists to solve this kind of problems, one of these methods by using the LU decomposition of matrix which is a good alternative to matrix inversion. The LU matrices are two matrices, the L matrix, which is a lower triangular matrix, and the U matrix, which is an upper triangular matrix. In this paper, a design of dual-core processor is used as the hardware of the work and certain software was written to enable the two cores of the dual-core processor to work simultaneously in computing the value of the L matrix and U matrix. The result of this work are compared with other works that using single-core processor, and the results found that the time required in the cores of the dual-core is more less than using single-core. The designed dual-core processor is invoked using the VHDL language. - Hybrid branch prediction for pipelined MIPS processor
Ali S. Al-Khalid and Safaa S. Omran
Institute of Advanced Engineering and Science
In the modern microprocessors that designed with pipeline stages, 
 the performance of these types of processors will be affected when executing branch instructions, because in this case there will be stalls in the pipeline. In turn this causes in reducing the Cycle Per Instruction (CPI) of the processor. In the case of executing a branch instruction, the processor needs an extra clocks to know if that branch will happen (Taken) or not (Not Taken) and also it requires calculating the new address in the case of the branch is Taken. The prediction that the branch is T / NT is an important stage in enhancing the processor performance. In this research more than one method of branch prediction (hybrid) is used and the designed circuit will choose different types of prediction algoritms depending on the type of the branch. Some of these methods were used are static while the other are dynamic. All circuits were built practically and examined by applying different programs on the designed predictor algorithm to compute the performance of the processor. - A shortest data window algorithm for detecting the power factor in presence of non-sinusoidal load current
Safaa S. Omran, Ali Sh. Al-Khalid, and Amer Atta Yaseen
Institute of Advanced Engineering and Science
During recent years, nonlinear power electronic equipments introduce harmonic pollution on electric power systems. It makes the traditional power factor meter can not act accurately when it monitors unbalanced and harmonic loads. In this paper, a new algorithm for detecting the power factor in presence of non-sinusoidal load current is proposed. The proposed algorithm detects the true power factor exactly. By uses only two successive sampled data points of the voltage and the current for each displacement power factor value calculation and two sampled data points for each distortion power factor value calculation, the total/true power factor becomes easy to measure using these values directly. The proposed detector implemented using microcontroller as a main part and has been tested for single phase power system. The test results show that it can measure the true power factor of the loads quickly and accurately. - Selective branch prediction schemes based on FPGA MIPS processor for educational purposes
H S Mahmood and S S Omran
IOP Publishing - Comparative Study between Different Rectangle Iris Templates
Safaa S. Omran and Aqeel A. Al-Hilali
IEEE - Implementation of LRU Replacement Policy for Reconfigurable Cache Memory Using FPGA
Safaa S. Omran and Ibrahim A. Amory
IEEE - Fast QR Decomposition Based on FPGA
Safaa S. Omran and Ahmed K. Abdul-abbas
IEEE - Design and implementation of 32-Bits MIPS processor to Perform QRD Based on FPGA
Safaa S. Omran and Ahmed K. Abdul-abbas
IEEE - Design of 32-bits RISC processor for hardware efficient QR decomposition
Safaa S. Omran and Ahmed K. Abdul-abbas
IEEE - Implementation of 4-way Superscalar Hash MIPS Processor Using FPGA
Safaa Sahib Omran and Laith Fouad Jumma
IOP Publishing - Multi core processor for QR decomposition based on FPGA
Safaa S. Omran and Ahmed K. Abdul-abbas
Science Publishing Corporation
Hardware design of multicore 32-bits processor is implemented to achieve low latency and high throughput QR decomposition (QRD) based on two algorithms which they are Gram Schmidt (GS) and Givens Rotation (GR). The orthogonal matrices are computed using the first core processor by Gram Schmidt algorithm, and the upper triangular matrices are computed using the second core processor by Givens Rotation algorithm. This design of multicore processor can achieve 50M QRD/s throughput for (4 × 4) matrices at running frequency 200 MHz. - Design of multithreading SHA-1 & SHA-2 MIPS processor using FPGA
Safaa S. Omran and Laith F. Jumma
IEEE - Iraqi car license plate recognition using OCR
Safaa S. Omran and Jumana A. Jarallah
IEEE - Design of SHA-1 & SHA-2 MIPS processor using FPGA
Safaa S. Omran and Laith F. Jumma
IEEE - Iraqi License Plate Localization and Recognition System Using Neural Network
Safaa S. Omran and Jumana A. Jarallah
IEEE - Reconfigurable cache memory architecture design based on VHDL
Safaa S. Omran and Ibrahim A. Amory
IEEE - Design of two dimensional reconfigurable cache memory using FPGA
Safaa S. Omran and Ibrahim A. Amory
IEEE - Quarter of Iris Region Recognition Using the RED Algorithm
Safaa S. Omran and Aqeel A. Al-Hillali
IEEE - Pipelined MIPS processor with cache controller using VHDL implementation for educational purposes
Hadeel Sh. Mahmood and Safaa S. Omran
IEEE - VHDL prototyping of a 5-stages pipelined RISC processor for educational purposes
- A very fast power factor calculation method
Ali. Sh. Al-Khalid and Safaa. S. Omran
IEEE - A cryptanalytic attack on Vigenère cipher using genetic algorithm
S. S. Omran, A. S. Al-Khalid, and D. M. Al-Saady
IEEE - Using genetic algorithm to break a mono - Alphabetic substitution cipher
S S Omran, A S Al-Khalid, and D M Al-Saady
IEEE
RECENT SCHOLAR PUBLICATIONS
- Design and implementation of dual-core MIPS processor for LU decomposition based on FPGA
RS Khalil, SS Omran
International Journal of Electrical and Computer Engineering (IJECE) 11 (2 2021 - Cache coherency controller for MESI protocol based on FPGA
MK Faeq, SS Omran
International Journal of Electrical and Computer Engineering 11 (2), 1043 2021 - Hybrid branch prediction for pipelined MIPS processor
AS Al-Khalid, SS Omran
International Journal of Electrical and Computer Engineering 10 (4), 3476 2020 - Design and Implementation of MIPS Processor for LU Decomposition based on FPGA
RS Khalil, SS Omran
European Journal of Electrical Engineering and Computer Science 4 (3) 2020 - Ultra fast frequency independent instantaneous power factor detector
SS Omran, AS Al-Khalid, AA Yaseen
International Journal of Power Electronics and Drive Systems 10 (4), 1961 2019 - A shortest data window algorithm for detecting the power factor in presence of non-sinusoidal load current
SS Omran, AS Al-Khalid, AA Yaseen
International Journal of Electrical and Computer Engineering 9 (5), 3956 2019 - Selective branch prediction schemes based on FPGA MIPS processor for educational purposes
HS Mahmood, SS Omran
IOP Conference Series: Materials Science and Engineering 518 (4), 042008 2019 - Comparative Study Between Different Rectangle Iris Templates
SS Omran, AA Al-Hilali
2018 International Conference on Advanced Science and Engineering (ICOASE), 7-12 2018 - Fast QR decomposition based on FPGA
SS Omran, AK Abdul-Abbas
2018 International Conference on Advanced Science and Engineering (ICOASE 2018 - Implementation of LRU replacement policy for reconfigurable cache memory using FPGA
SS Omran, IA Amory
2018 International Conference on Advanced Science and Engineering (ICOASE 2018 - Automatic IRAQI cars number plates extraction
SS Omran, JA Jarallah
Iraqi Journal for Computers and Informatics Vol 44 (1), 34-41 2018 - Design of 32-bits RISC processor for hardware efficient QR decomposition
SS Omran, AK Abdul- abbas
2018 International Conference on Advances in Sustainable Engineering and 2018 - Design and implementation of 32-Bits MIPS processor to Perform QRD Based on FPGA
SS Omran, AK Abdul-abbas
2018 International Conference on Engineering Technology and their 2018 - Implementation of 4-way Superscalar Hash MIPS Processor Using FPGA
SS Omran, LF Jumma
Journal of Physics: Conference Series 1003 (1), 012037 2018 - Implementation QR decomposition based on triangular systolic array
S Omran, AK Abdul-Abbas
Int. J. New Technol. Sci. Eng 5 (6), 150-161 2018 - Multi core processor for QR decomposition based on FPGA
SS Omran, AK Abdul-abbas
International Journal of Engineering & Technology 7 (4), 2100-2105 2018 - Design and implementation of high speed arithmetic processor
SS Omran, AK Abdul-abbas
International Journal of Applied Engineering Research 13 (11), 9167-9171 2018 - Iraqi License Plate Localization and Recognition System Using Neural Network
SS Omran, JA Jarallah
2017 Second Al-Sadiq International Conference on Multidisciplinary in IT and 2017 - Reconfigurable cache memory architecture design based on VHDL
SS Omran, IA Amory
2017 International Conference on Electrical and Computing Technologies and 2017 - Design of multithreading SHA-1 & SHA-2 MIPS processor using FPGA
SS Omran, LF Jumma
2017 8th International Conference on Information Technology (ICIT), 632-637 2017
MOST CITED SCHOLAR PUBLICATIONS
- Iraqi Car License Plate Recognition Using OCR
SS Omran, JA Jarallah
NTICT, 298-303 2017
Citations: 45 - A cryptanalytic attack on Vigenre cipher using genetic algorithm
SS Omran, AS Al-Khalid, DM Al-Saady
2011 IEEE Conference on Open Systems, 59-64 2011
Citations: 39 - Using genetic algorithm to break a mono-alphabetic substitution cipher
SS Omran, AS Al-Khalid, DM Al-Saady
2010 IEEE Conference on Open Systems (ICOS 2010), 63-67 2010
Citations: 26 - Implementation of LRU replacement policy for reconfigurable cache memory using FPGA
SS Omran, IA Amory
2018 International Conference on Advanced Science and Engineering (ICOASE 2018
Citations: 14 - Quarter of Iris Region Recognition Using the RED Algorithm
SS Omran, AA Al-Hillali
2015 17th UKSim-AMSS International Conference on Modelling and Simulation 2015
Citations: 13 - Using genetic algorithms to break a simple transposition cipher
AS Al-Khalid, SS Omran, DA Hammood
6th International conference on information technology ICIT 2013
Citations: 13 - ECG Rhythm Analysis by Using Neuro-Genetic Algorithms
SS Omran, SMR Taha, NA Awadh
MASAUM Journal of Basic and Applied Sciences 1 (3) 2009
Citations: 13 - Automatic IRAQI cars number plates extraction
SS Omran, JA Jarallah
Iraqi Journal for Computers and Informatics Vol 44 (1), 34-41 2018
Citations: 9 - Design of 32-bits RISC processor for hardware efficient QR decomposition
SS Omran, AK Abdul- abbas
2018 International Conference on Advances in Sustainable Engineering and 2018
Citations: 9 - Iraqi License Plate Localization and Recognition System Using Neural Network
SS Omran, JA Jarallah
2017 Second Al-Sadiq International Conference on Multidisciplinary in IT and 2017
Citations: 9 - Design and implementation of 32-Bits MIPS processor to Perform QRD Based on FPGA
SS Omran, AK Abdul-abbas
2018 International Conference on Engineering Technology and their 2018
Citations: 8 - design of sha-1 &sha-2 mips processor using fpga
safaa s omran, L jumma
NTICT, 268-273 2017
Citations: 8 - Design of multithreading SHA-1 & SHA-2 MIPS processor using FPGA
SS Omran, LF Jumma
2017 8th International Conference on Information Technology (ICIT), 632-637 2017
Citations: 7 - Design of two dimensional reconfigurable cache memory using FPGA
SS Omran, IA Amory
2016 5th International Conference on Electronic Devices, Systems and 2016
Citations: 7 - Design and implementation of multi-model biometric identification system
SS Omran, MA Salih
International Journal of Computer Applications 99 (15), 14-21 2014
Citations: 7 - Hardware modelling of a 32-bit, single cycle RISC processor using VHDL
SS Omran, HS Mahmood
ICIT 2013 The 6th International Conference on Information Technology 2013
Citations: 7 - Fast QR decomposition based on FPGA
SS Omran, AK Abdul-Abbas
2018 International Conference on Advanced Science and Engineering (ICOASE 2018
Citations: 6 - FPGA Implementation of MIPS RISC Processor for Educational Purposes
SS Omran, AJ Ibada
Journal of Babylon University/Pure and Applied Sciences 24 (7), 1745-1761 2016
Citations: 6 - Using an FPGA to Accelerate Iris Recognition
SS Omran, A Al-Hilali
ICSCME'2015, 55-62 2015
Citations: 6 - Cache coherency controller for MESI protocol based on FPGA
MK Faeq, SS Omran
International Journal of Electrical and Computer Engineering 11 (2), 1043 2021
Citations: 5