A novel fusion switching pattern generation algorithm for "N-Level" switching angle algorithm based trinary cascaded hybrid multi-level inverter Joseph Anthony Prathap, T.S. Anandhi Power Converters Drives and Controls for Sustainable Operations, 2024 This chapter presents a novel fusion algorithm, the Switching Angle Algorithm, with no carrier to produce Digital Pulse Width Modulation control for the “N”-level Trinary Cascaded Hybrid MLI circuit. The proposed fusion Switching Patterns Generation algorithm includes experimental evaluation of the Digital PWM using the Field Programmable Gate Array for the “N”-level Trinary Cascaded Hybrid MLI. The TCHMLI with non-carrier based SAA utilizes unequal DC values with trinary progression. The advantages of TCHMLI are higher voltage levels with minimum switches, a decrease in %THD by achieving an increased level in MLI, low distortion output response without filters, optimized power processing of the overall system, and easy implementation using digital controllers. Conventionally, the generation of switch patterns for the Multi-Level Inverter uses the sine wave as modulating signal and high-frequency triangular wave as a carrier signal, whereas the non-carrier Switching Angle Algorithms (SAA) utilize the events at which the MLI levels change. Based on the event angle, the SAA is classified as: i) Equal Phase-SAA (EP-SAA), ii) Half Equal Phase-SAA (HEP-SAA), iii) Feed Forward-SAA (FF-SAA), and iv) Half Height-SAA (HH-SAA). Among these four methods, the HH-SAA method proves to be advantageous for parametric analysis like THD%, V RMS , and V PEAK . The events of switching change based on the voltage steps of the inverter circuit. Generally, the n-levels of the MLI circuit demands (n-1)/2 events of switching in each quadrant and 2(n-1) events of switching for one cycle with a frequency of 50Hz. The simulations of the HH-SAA-Trinary Cascaded MLI for the “N”-level are manipulated by the System Generator model and the parametric analysis is validated with an FPGA device. The fusion algorithm involves the combination of the Digital Switching Function and Digital PWM using VHDL. The DSFG and DSPG blocks are coded using the behavioral style of VHDL coding for all the “N”-levels of TCHMLI.
Modelling, Simulation, and Implementation of Effective Controller for KY Stepping Up Converter K. Ramash Kumar, T. S. Anandhi, B. Vijayakrishna, S. Balakumar Modelling and Simulation in Engineering, 2022 This paper studies on a new Hybrid Posicast Control (HPC) for Fundamental KY Boost Converter (FKYBC) worked in Continuous Current Mode (CCM). Posicast is a feed-forward compensator. It reduces the overshoot in the step result of the flippantly damped plant. But the conventional controller approach is sensitive owing to the changes in the natural frequency. So, as to reduce this undesirable sensitivity and load potential control of FKYBC, a HPC is designed in this article. Structure of HPC is posicast with feedback loop. The independent computational time delay is the main design function of the posicast. The enactment of the FKYBC with HPC is confirmed at various operating regions by making the MATLAB/Simulink and experimental model. The posicast function values are implemented in Arduino Uno-ATmega328P microcontroller. The results of new HPC have produced minimal noise in control signal in comparison with traditional PID control.
Modified Mechanical Structure Electric Bike Design Computation and Prototype Model Implementation K. Ramash Kumar, T. S. Anandhi, B. Vijayakrishna, Monalisa Mohanty, M. Siva Ramkumar, H. A. Shivappa, Belachew Zegale Tizazu, B. Kirubakaran, E. Thinapakar Advances in Materials Science and Engineering, 2021 The aim of this paper is to investigate the design computation and prototype model implementation of a Modified Mechanical Structure (MMS) Electric Bike (E-Bike). It is the technology that allows the vehicle to operate with the assistance of electrical energy. All conventional cars will be converted to electric vehicles (EVs) in the future. EVs will be affordable to all types of people, allowing them to fly comfortably and safely. As a result, this paper proposes a design estimate and model implementation of the MMS E-Bike with the smallest number of parts, lowest expense, and lightest weight possible. The most important parts of the designed MMS E-Bike are the battery, MMS, BLDC motor, and electronic commutator with their controller. Because of its adapted mechanical frame nature, the designed E-Bike is low in cost and weight, and it can also go up to 25 kmph. Furthermore, the rider will be able to ride the built MMS E-Bike without any pain to their bodies and should be able to sit comfortably during their journey. In comparison to the Ampere Angel and DMW Electra 20 E-Bikes, the performance of the developed model is tested under various operating conditions, as well as their battery backup.
A novel parallel duty cycle control algorithm for photovoltaic voltage regulator system using FPGA Joseph Anthony Prathap, T.S. Anandhi Microprocessors and Microsystems, 2019 In this paper, a novel parallel duty cycle control method is proposed to regulate the load voltage of the photo voltaic (PV) fed DC-DC buck converter. The proposed method concentrates on the control of PV fed DC-DC buck converter by fusing the two duty cycles from maximum power point tracking (MPPT) and digital proportional integral-digital pulse width modulation (DPI-DPWM) through the HDPWM algorithm. The fusion of the MPPT algorithms and DPI-DPWM algorithms achieve high precision in the voltage regulation of the PV fed DC-DC buck converter. The proposed parallel duty cycle control is passed through the HDPWM algorithm to compensate the high clocking frequency demand with the design resolution of 210 bits. Further, the design complexity of the HDPWM algorithm is reduced as the resolution of 210 bits is split as 25 and 25 bits for CDPWM and DDPWM respectively. The FPGA based implementation of the proposed parallel duty cycle method includes the synthesizable VHDL code for i) MPPT algorithms, ii) DPI-based DPWM algorithms, iii) Fusing of the MPPT-DPI-DPWM and iv) Passing the fused MPPT-DPI-DPWM through the HDPWM algorithm. The Xilinx Spartan 3A DSP, FPGA implementation is suitable for the proposed parallel duty cycle control method. The hardware results validate the satisfactory PV voltage regulation under continuous changing weather conditions. The transient response of INC-DPI-HDPWM seems to have a faster settling time compared to other MPPT-DPI-DPWM methods. Also, its FPGA implementation proves less area in design and low power consumption compared to the existing methods.
Investigation of FPGA based 32-bit RISC-modulation processor International Journal of Computer Information Systems and Industrial Management Applications, 2018
Performance evaluation and analysis of 64-quadrature amplitude modulator using Xilinx Spartan FPGA International Journal of Engineering and Technology Uae, 2018
Multi image integration and Encryption Algorithm for security applications A.D. Senthil Kumar, T.S. Anandhi IECON Proceedings Industrial Electronics Conference, 2016 This paper focuses on implementing a secure image technique that enables to select one of the several images displayed simultaneously with a unique security key for each image. This process involves applying block based interleaving, followed by integrating the image matrix using the pixel based integration technique and encrypting the images with Advanced Encryption Algorithm. With the key specifically generated for the image, the original image is decrypted from multiple images. This method is useful when access permissions needs to be restricted to certain viewers.
A design and implementation of hybrid controller for 3 phase to 3 phase power conversion using matrix converter International Journal of Applied Engineering Research, 2015
Real time implementation of multi carrier based PWM techniques for single phase nine level trinary source CMLI using dSPACE International Review on Modelling and Simulations, 2013
Performance evaluation of real time implementation of new hybrid PWM strategies for single phase seven level asymmetrical inverter International Review of Electrical Engineering, 2013
Circuit level comparison of single- phase five- level inverters Proceedings of the International Conference on Power Electronics and Drive Systems, 2005
RECENT SCHOLAR PUBLICATIONS
An integrated review on the role of different biocatalysts, process parameters, bioreactor technologies and data-driven predictive models for upgrading biogas P Mullai, SM Sambavi, S Vishali, K Dharmalingam, S Sutha, S Dinesh, ... Journal of Environmental Management 384, 125508 , 2025 2025 Citations: 4
A Novel Fusion Switching Pattern Generation Algorithm for “N-Level” Switching Angle Algorithm Based Trinary Cascaded Hybrid Multi-Level Inverter JA Prathap, TS Anandhi Power Converters, Drives and Controls for Sustainable Operations, 203 , 2023 2023
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Simulation and dSPACE based implementation of various PWM strategies for a new H-type FCMLI topology CR Balamurugan, SP Natarajan, B Shanthi, TS Anandhi International Journal of Power Electronics and Drive System 6 (3), 615-624 , 2015 2015 Citations: 8
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UC3907 ASIC and TMS320F2407A DSP based control of paralleled Buck DC-DC converters TS Anandhi, SP Natarajan, T Anitha 2005 Annual IEEE India Conference-Indicon, 472-475 , 2005 2005 Citations: 4