Mohankumar Mylsamy

@sece.ac.in

Assistant Professor
Sri Eshwar College of Engineering, Coimbatore, Tamilnadu, INDIA

Mohankumar Mylsamy


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https://researchid.co/mohanyaso

RESEARCH, TEACHING, or OTHER INTERESTS

Electrical and Electronic Engineering, Engineering, Artificial Intelligence, Multidisciplinary
26

Scopus Publications

136

Scholar Citations

5

Scholar h-index

4

Scholar i10-index

Scopus Publications

  • Advances and Trends in Low-Power Logic-Compatible Phase Change Memory (PCM): A Comprehensive Survey
    Saranyanandhini D, Shanmugasundaram N, Mohan Kumar M, Nandhini M
    2026 2nd International Conference on Intelligent Systems for Communication Iot and Security Iciscois 2026, 2026
    Phase Change Memory (PCM) is a non-volatile technology which has received significant interest as a next-generation compute in-memory technology and artificial intelligence, as well as a high performance and energy efficient embedded system. This paper contains an in-depth experimental study of lowpower, logic compatible 40 nm PCM cells, principally regarding their reliability, reliability, and compatibility with neuromorphic and artificial intelligence devices. The wide characterization of the devices included endurance cycling, resistance drift experiments, high temperature data retention tests, and variability tests. At 120° C, retention studies indicate that with a heat of more than 120° C a memory life of more than ten years is observed and endurance tests indicates good performance up to 200,000 program/erase cycles with no memory window erosion. The measurements of drift in high resistance and low resistance stages reflect the resistance development that is well controlled and statistical measures confirm narrow distributions that are vital to stable operation and multi-level programming. The potential of PCM arrays is also validated by analysis in binary neural network models, wherein the robustness of the performance of the simulated inference distributions is obtained with simulated noise and unpredictability in the devices. On the whole, the results make low power PCM one of the leaders in embedded and artificial intelligence computing systems that offer scalable integration of the system, a high endurance level, precise programmability, and long term data retention.
  • Comparative Analysis on Cold CMOS in Advanced FinFET Technology at 300 K and 77 K
    Mohanapriya K, Shanmugapriya A, Mohankumar M, Saranyanandhini D
    Proceedings of the 4th IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation Iatmsi 2026, 2026
    This work investigates the behavior of CMOS circuits operating at low temperature using advanced FinFET technology. A comparative study is carried out between room temperature operation at 300 K and cryogenic operation at 77 K to understand the impact of temperature scaling on device and circuit performance. As CMOS devices continue to scale, issues such as leakage power, thermal noise, and performance variability have become critical challenges, especially for high-speed and low-power applications. Operating transistors at cryogenic temperatures helps reduce these effects by improving carrier mobility and suppressing leakage mechanisms. In this study, physics-based simulations are performed to extract important device parameters including drive current, leakage current, threshold voltage, subthreshold swing, and transconductance under different bias conditions. In addition, interconnect effects are considered to evaluate changes in wire resistance and signal delay at low temperature. Circuit-level analysis using a FinFET-based CMOS inverter is used to examine delay and power consumption. The results show noticeable improvement in switching speed and a significant reduction in leakage and power dissipation at 77 K. Overall, the combined device, interconnect, and circuitlevel analysis confirms that cryogenic FinFET CMOS operation is a promising approach for future lowpower and high-performance systems, particularly in applications such as quantum control electronics and cryogenic computing platforms.
  • Design of Precise and Efficient BCD Adders Using Majority Gate Full Adder for Quantum Cellular Automata
    Mohanapriya K, Abirami V, Shanmugapriya A, Mohankumar M, Saranyanandhini D
    Proceedings of the 4th IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation Iatmsi 2026, 2026
    The binary coded-decimal arithmetic logic is necessary where extreme accuracy and precision are needed in applications, image processing, telecommunications, and such as computation digital signal processing. Quantum Cellular Automata technology is a promising platform on which an efficient design can be developed. In this paper, the design of different specific and effective is introduced. Majority gate full adder Binary Coded Decimal adders, to Quantum Cellular Automata implementation. The proposed design has fewest required number of cells, interconnections, to guarantee less complexity and power usage. The BCD addition is efficiently computed by optimized majority gate and without losing logical correctness and good performance. Comparative analysis with the available designs brings forth. This work shows the possibility of incorporating high-level majority. QCA gate logic of scalable and high-performance arithmetic circuits.
  • Low Frequency Single Cycle Multi-Hop NoCs for High Performance and Energy Efficiency
    Mohammed Adhil H, Mohankumar M
    2025 IEEE International Conference on Modern Electronics Devices and Intelligent Communication Systems Medcom 2025, 2025
    The rapid growth in the size of modern multicore processors in terms of the number of cores has increased the need to have effective on-chip communication systems. The conventional Network-on-Chip (NoC) architecture has serious scalability challenges because of the enhanced latency and energy dissipation incurred by the quantity of hops between communication cores. Current methods usually entail tradeoffs, to make SMART NoCs and traditional Dynamic Voltage and Frequency Scaling (DVFS) methods tend to make higher energy efficiency of a system, or express links and high-radix routers to make less energy consumption more energy-consuming. This paper presents a new low-frequency single-cycle multi-hop (LFSCH) NoC architecture that will be used to design the architecture focused on improving the performance and energy efficiency. The most important innovation that allows operating DVFS efficiently and at the same time ensures single-cycle multi-hop traversal is the separation of router and link frequencies. The suggested design is simulated and simulated under varying frequency combinations and workloads with the help of Gem5 simulation framework. Experimentation suggests that the LFSCH NoC provides between 28% and 17% greater energy efficiency and 17% lower latency than other NoC architectures and would be sensible option in scalable and energy efficient multi-cores.
  • LOW POWER DESIGN OF SPI AND I2C PROTOCOL IN VERILOG HDL
    Mohanapriya K., Mohankumar M., Suganya L.
    Suranaree Journal of Science and Technology, 2025
    A method for sharing data between a slave and a master is the SPI (Serial Peripheral Interface). The result of this paper explores a high-speed SPI configuration that utilizes clock gating, drawing inspiration from Motorola’s manual and is implemented in Xilinx’s Virtex 5 FPGA using Verilog 2001. It covers design strategies for managing the SPI bus, including handling multiple slave devices. The document also explores an I2C (Inter-Integrated Circuit) single master with a bidirectional data line, supporting multiple masters and efficient communication between devices. The I2C master can transfer numerous bytes of data, controlled through a start signal and slave address. The design is in Verilog, simulated with Xilinx Vivado, and is parameterized for flexibility. The goal is to provide a deep understanding of SPI and I2C protocols, their applications, and implementation in FPGA devices, along with insights into their design and simulation process.
  • Efficient AI Accelerator based on Systolic Array Architecture with Approximate Computing Techniques
    Gayathri Devi B, RamKumar S, Mohan Kumar M
    Proceedings of 6th International Conference on Iot Based Control Networks and Intelligent Systems Icicnis 2025, 2025
    This paper introduces an optimized AI accelerator that combines a systolic array architecture with approximate computing to achieve high performance and low power consumption. The architecture targets energy efficiency and hardware optimization by integrating controlled approximations into the arithmetic operations of each Processing Element (PE). In this design, the multiplier unit incorporates approximate compressors and adders, while a Constant-OR Adder (COA) is implemented in the least significant bit (LSB) region of the adder to minimize logic depth and switching activity. These enhancements significantly reduce the overall critical path delay, silicon area, and power usage while maintaining reliable computational accuracy for AI and deep learning tasks. The systolic array framework ensures synchronized data flow through multiple PE arrays and columns, supporting parallel and pipelined matrix operations. Additionally, the use of a 16-register data management scheme improves data reuse and accelerates processing throughput. Experimental and synthesis results reveal that the proposed approximate systolic array outperforms conventional exact designs, achieving substantial reductions in delay, area, and energy consumption. The outcomes confirm that small arithmetic approximations can yield major efficiency gains without degrading output quality. Consequently, this design represents a promising approach for developing compact, high-speed, and power-aware AI accelerators suitable for edge and embedded intelligent systems.
  • Quantum Algorithms and Their Applications in Cryptology: A Practical Approach
    Bhupendra Singh, Mohankumar Mylsamy, Thamaraimanalan Thangarajan
    Quantum Algorithms and their Applications in Cryptology A Practical Approach, 2025
    Cryptography has long been an essential tool in safeguarding digital communication and securing sensitive information. As technology has progressed, so has the complexity of the methods used to protect our data. In the wake of quantum computing's rise, traditional cryptographic systems face serious challenges, demanding a new understanding of how quantum algorithms could both undermine and enhance security. Chapter 1 deals with the Basics of Cryptography lays the groundwork by introducing classical cryptography, tracing its evolution from ancient ciphers to modern cryptosystems. In Chapter 2, readers are introduced to Quantum Algorithms, the principles of quantum mechanics relevant to computing, including qubits, superposition, and entanglement. The Chapter 3 focuses on Shor’s algorithm, a landmark quantum algorithm that threatens the security of widely used public-key cryptosystems like RSA and ECC. In Chapter 4 Grover’s Algorithm is examined in the context of brute-force attacks on symmetric key cryptography. Chapter 5 focusing on Simon’s Algorithm and its role in breaking cryptographic primitives through structure exploitation. In Chapter 6 a broader discussion about Cryptographic Implications of Quantum Computing is given on how quantum computing affects modern cryptographic systems. Finally, in Chapter 7, the future of cryptography in the quantum era is discussed.
  • HDL Implementation of DES Algorithm for Telecommunication Applications
    Saranyanandhini D, Nivethitha T, MohanKumar M
    Proceedings of 3rd International Conference on Augmented Intelligence and Sustainable Systems Icaiss 2025, 2025
    The increasing need for secure data transmission in telecommunications networks has made hardware-level implementation of effective encryption algorithms crucial. This paper introduces an implementation of the Data Encryption Standard (DES) algorithm in Hardware Description Language (HDL) that is tailored for use in telecommunications. For real-time, fast data transfer, the suggested architecture is appropriate since it maximizes resource usage while guaranteeing strong encryption. By using an HDL-based design, the encryption module has improved speed, decreased latency, and effectively managed hardware resources. Based on experimental results, the suggested HDL implementation is a workable way to safeguard sensitive data in contemporary telecommunication networks since it strikes a balance between security, processing speed, and area efficiency. In addition to providing insights into safe and effective communication circuit design, this work demonstrates the viability of utilizing DES in hardware-based encryption for telecommunication systems.
  • Modeling and Benchmarking of High-Speed and Low-Power Spin-Orbit-Torque Magnetic Random-Access Memory (SOT-MRAM) Using MATLAB
    Sharmila Parveen M, Mohankumar M, Shivanandham R S
    2025 7th International Symposium on Advanced Electrical and Communication Technologies Isaect 2025, 2025
    Spin Orbit Torque Magnetic Random-Access Memory (SOT-MRAM) has emerged as a promising candidate for next-generation non-volatile memory, offering high-speed operation, low write energy, and excellent endurance. In this work, we present a comprehensive modeling and benchmarking framework for a two-terminal SOT-MRAM device that uses MATLAB. The model integrates a macrospin-based spin-transport formulation with thickness-dependent spin-diffusion effects and a parametric FinFET drive circuit, enabling co-optimization of device and circuit parameters. Benchmarking is carried out for three key SOT materials -β-W, Pt, and Bi<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf>Se<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1−x</inf> considering variations in resistivity, spin Hall angle, and spin-diffusion length. The analysis includes switching current, energy consumption, and number of fin scaling as functions of SOT layer thickness. Furthermore, energy–delay trade-offs, thermal stability and retention characteristics, VCMA-assisted switching, and field-like torque contributions are investigated to assess the performance–reliability balance. Simulation results demonstrate that optimized β-W and Bi<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf>Se<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1−x</inf> structures achieve sub-femtojoule switching energy with sub-nanosecond delay, highlighting their potential for embedded and high-speed cache memory applications. The suggested framework offers a flexible design and benchmarking system for the quick analysis of the emerging SOT-MRAM technologies.
  • Optimized Design of Clock-Gated D Flip-Flop using Transmission Gate
    Jeevitha R, Mohankumar M, Gayathri Devi B, Mohammed Adhil H
    Proceedings of 3rd International Conference on Augmented Intelligence and Sustainable Systems Icaiss 2025, 2025
    Modern digital applications will call for very fast and optimum devices because they are associated with minimal delay and power. Through a transmission gate, the proposed design employs a low-power clock pulsed data flip-flop (D flip-flop). This study proposes to use the clock gating technique to design a low-power pulsed D flip-flop. By reducing transistor switching, the gated clock reduces the circuit's dynamic power usage. One of the methods of applying clock gating is to disrupt the circuit’s clock input using an OR gate in relation to the signal Enable. This method makes the clock idle to reduce power consumption when the output is at a particular steady state. This research therefore puts forth a concept of a clock-pulsed low power D Flip Flop (DFF) structural design based on the use of transmission gates to enhance the power efficiency of digital circuits. The proposed DFF is intended for constructing a 4-bit serial in parallel-out shift register to show the efficient performance of low power applications. The cadence tool with 90nm technology is also used to simulate all the designs and what is observed is that the tool provides better power, number of transistors, and delay efficiency.
  • Machine Learning-Based Analysis of Lifestyle Factors for Sleep Apnea Detection
    M Nandhini, C Suganthi Evangeline, M Mohan Kumar, V Sureshkumar
    2025 8th International Conference on Circuit Power and Computing Technologies Iccpct 2025, 2025
  • Simulation and Analysis Framework for STT-MRAM: Exploring Switching Dynamics, Energy Metrics, and System-Level Reliability
    Shivanandham R S, Shanmugasundaram N, Mohan Kumar M, Sharmila Parveen M
    IC Decon 2025 2025 International Conference on Data Energy and Communication Network Proceedings, 2025
  • Securing 6G Networks in the Quantum Age: The Role of Quantum Cryptography
    Nandhini M, C. Suganthi Evangeline, P. Emmanuel Joy, M. Karthiga, Mohan Kumar M
    Proceedings of 3rd International Conference on Intelligent Cyber Physical Systems and Internet of Things Icoici 2025, 2025
  • DESIGN AND ANALYSIS OF NOVEL PARALLEL PREFIX ADDERS FOR VLSI CIRCUITS
    Prabakaran Govindaraj, Shanmugasundaram Nallasamy, Mohankumar Mylsamy, Sathiyapriya Krishnamoorthy
    Suranaree Journal of Science and Technology, 2024
  • Performance Analysis of Shor's Algorithm for Integer Factorization Using Quantum and Classical Approaches
    T. Thamaraimanalan, Bhupendra Singh, M. Mohankumar, Santosh Kumar Korada
    10th International Conference on Advanced Computing and Communication Systems Icaccs 2024, 2024
  • Quantum Key Recovery Attack on Simplified Grain 4-Bit Cipher Using Grover's Algorithm
    M MohanKumar, Bhupendra Singh, T Thamaraimanalan, Santosh Kumar Korada, P Yuvaraj, S Jyothikamalesh
    10th International Conference on Advanced Computing and Communication Systems Icaccs 2024, 2024
  • Efficient VQE Approach for Accurate Simulations on the Kagome Lattice
    S. Jyothikamalesh, A. Kaarnika, M. Mohankumar, Sanjay Vishwakarma, Srinjoy Ganguly, P. Yuvaraj
    Communications in Computer and Information Science, 2024
  • Experimental Analysis on SVM-based Image Classifiers for Medical Applications
    C. Venkataramanan, M. Mohankumar, K. Mohanapriya, K.G. Kamalisri, M. Karunya, L. Suganya
    2023 2nd International Conference on Advances in Computational Intelligence and Communication Icacic 2023, 2023
  • Depiction of FPGA Based Vending Machine Using Mealy Model
    Sathiyapriya. K, Nirmala. P, Deepika. M, Revanth. J, Saravanan. M, Mohankumar. M
    Proceedings of the 3rd International Conference on Smart Technologies in Computing Electrical and Electronics Icstcee 2022, 2022
  • Certain Investigations on Adder Design for VLSI Signal Processing
    Sathiyapriya. K, Nirmala. P, Mohanapriya. S, Rahul.S. S, T. Thamaraimanalan, M. Mohankumar
    8th International Conference on Advanced Computing and Communication Systems Icaccs 2022, 2022
  • Machine Learning based Patient Mental Health Prediction using Spectral Clustering and RBFN Algorithms
    T. Thamaraimanalan, M. Mohankumar, H. Anandakumar, M. Deepha, U. Hari Priya, G. Bhanu Priya, M. Aiswarya Devi
    8th International Conference on Advanced Computing and Communication Systems Icaccs 2022, 2022
  • Experimental analysis of intelligent vehicle monitoring system using Internet of Things (IoT)
    T. Thamaraimanalan, M. Mohankumar, S. Dhanasekaran, H. Anandakumar
    Eai Endorsed Transactions on Energy Web, 2021
  • A low power VLSI implementation of distortion correction in image processing ASIC
    M. Mohankumar, V. Gopalakrishnan, S. Yasotha
    International Journal of Biomedical Engineering and Technology, 2018
  • Innovation in the operation of UAV sensors
    B. S. M. Augustine, M. Mohankumar, T. M. Yoga Anandh
    Advances in Intelligent Systems and Computing, 2017
  • Multi-sink Optimal Repositioning for Energy and Power Optimization in Wireless Sensor Networks
    S. Yasotha, V. Gopalakrishnan, M. Mohankumar
    Wireless Personal Communications, 2016
  • A vlsi approach for distortion correction in surveillance camera images
    Arpn Journal of Engineering and Applied Sciences, 2015

RECENT SCHOLAR PUBLICATIONS

  • Comparative Analysis on Cold CMOS in Advanced FinFET Technology at 300 K and 77 K
    K Mohanapriya, A Shanmugapriya, M Mohankumar, D Saranyanandhini
    2026 IEEE International Conference on Interdisciplinary Approaches in … , 2026
    2026
  • Design of Precise and Efficient BCD Adders Using Majority Gate Full Adder for Quantum Cellular Automata
    K Mohanapriya, V Abirami, A Shanmugapriya, M Mohankumar, ...
    2026 IEEE International Conference on Interdisciplinary Approaches in … , 2026
    2026
  • Modeling and Benchmarking of High-Speed and Low-Power Spin-Orbit-Torque Magnetic Random-Access Memory (SOT-MRAM) Using MATLAB
    M Mohankumar, RS Shivanandham
    2025 7th International Symposium on Advanced Electrical and Communication … , 2025
    2025
  • Quantum Algorithms and Their Applications in Cryptology: A Practical Approach
    B Singh, M Mylsamy, T Thangarajan
    CRC Press , 2025
    2025
  • Efficient AI Accelerator based on Systolic Array Architecture with Approximate Computing Techniques
    S RamKumar
    2025 6th International Conference on IoT Based Control Networks and … , 2025
    2025
  • Securing 6G Networks in the Quantum Age: The Role of Quantum Cryptography
    M Nandhini, CS Evangeline, PE Joy, M Karthiga
    2025 3rd International Conference on Intelligent Cyber Physical Systems and … , 2025
    2025
  • Machine Learning-Based Analysis of Lifestyle Factors for Sleep Apnea Detection
    M Nandhini, CS Evangeline, MM Kumar, V Sureshkumar
    2025 8th International Conference on Circuit, Power & Computing Technologies … , 2025
    2025
    Citations: 1
  • HDL Implementation of DES Algorithm for Telecommunication Applications
    D Saranyanandhini, T Nivethitha, M MohanKumar
    2025 Third International Conference on Augmented Intelligence and … , 2025
    2025
  • Optimized Design of Clock-Gated D Flip-Flop using Transmission Gate
    R Jeevitha, M Mohankumar, B Gayathri Devi, H Mohammed Adhil
    2025 Third International Conference on Augmented Intelligence and … , 2025
    2025
  • LOW POWER DESIGN OF SPI AND I2C PROTOCOL IN VERILOG HDL.
    K Mohanapriya, M Mohankumar, L Suganya
    Suranaree Journal of Science & Technology 32 (1) , 2025
    2025
  • Performance Analysis of Shor's Algorithm for Integer Factorization Using Quantum and Classical Approaches
    T Thamaraimanalan, B Singh, M Mohankumar, SK Korada
    2024 10th International Conference on Advanced Computing and Communication … , 2024
    2024
    Citations: 12
  • Quantum Key Recovery Attack on Simplified Grain 4-Bit Cipher Using Grover's Algorithm
    M MohanKumar, B Singh, T Thamaraimanalan, SK Korada, P Yuvaraj, ...
    2024 10th International Conference on Advanced Computing and Communication … , 2024
    2024
    Citations: 3
  • DESIGN AND ANALYSIS OF NOVEL PARALLEL PREFIX ADDERS FOR VLSI CIRCUITS.
    P Govindaraj, S Nallasamy, M Mylsamy, S Krishnamoorthy
    Suranaree Journal of Science & Technology 31 (1) , 2024
    2024
  • Experimental Analysis on SVM-based Image Classifiers for Medical Applications
    C Venkataramanan, M Mohankumar, K Mohanapriya, KG Kamalisri, ...
    2023 Second International Conference on Advances in Computational … , 2023
    2023
    Citations: 1
  • Efficient VQE approach for accurate simulations on the Kagome lattice
    S Jyothikamalesh, A Kaarnika, M Mohankumar, S Vishwakarma, ...
    International Conference on Artificial Intelligence and Knowledge Processing … , 2023
    2023
    Citations: 2
  • Efficient VQE approach for accurate simulations on the Kagome lattice
    S Vishwakarma, S Ganguly
    arXiv preprint arXiv:2306.00467 , 2023
    2023
    Citations: 1
  • Certain Investigations on Adder Design for VLSI Signal Processing
    T Thamaraimanalan, M Mohankumar
    2022 8th International Conference on Advanced Computing and Communication … , 2022
    2022
  • Machine Learning based Patient Mental Health Prediction using Spectral Clustering and RBFN Algorithms
    T Thamaraimanalan, M Mohankumar, H Anandakumar, M Deepha, ...
    2022 8th International Conference on Advanced Computing and Communication … , 2022
    2022
    Citations: 10
  • A Novel Undistorted Image Fusion and DWT Based Compression Model with FPGA Implementation for Medical Applications
    M Mohankumar, S Akilan, B Hariprasath, R Ariprasath, SD Dharsan
    2022
    Citations: 1
  • Multi-Parameter Smart Health Monitoring System Using Arduino-Uno
    M Mohankumar, PB Kirthana, M Shree, M Mylsamy
    Multi-Parameter Smart Health Monitoring System Using Arduino-Uno , 2022
    2022
    Citations: 2

MOST CITED SCHOLAR PUBLICATIONS

  • Experimental analysis of intelligent vehicle monitoring system using Internet of Things (IoT)
    T Thamaraimanalan, M Mohankumar, S Dhanasekaran, H Anandakumar
    EAI Endorsed Transactions on Energy Web , 2021
    2021
    Citations: 64
  • Performance Analysis of Shor's Algorithm for Integer Factorization Using Quantum and Classical Approaches
    T Thamaraimanalan, B Singh, M Mohankumar, SK Korada
    2024 10th International Conference on Advanced Computing and Communication … , 2024
    2024
    Citations: 12
  • Multi-sink optimal repositioning for energy and power optimization in wireless sensor networks
    S Yasotha, V Gopalakrishnan, M Mohankumar
    Wireless Personal Communications 87 (2), 335-348 , 2016
    2016
    Citations: 12
  • Machine Learning based Patient Mental Health Prediction using Spectral Clustering and RBFN Algorithms
    T Thamaraimanalan, M Mohankumar, H Anandakumar, M Deepha, ...
    2022 8th International Conference on Advanced Computing and Communication … , 2022
    2022
    Citations: 10
  • A VLSI APPROACH FOR DISTORTION CORRECTION IN SURVEILLANCE CAMERA IMAGES
    M.Mohankumar, S.Yasotha, V.Gopalakrishnan
    ARPN Journal of Engineering and Applied Sciences 10 (NO. 9), 4105-4108 , 2015
    2015
    Citations: 7
  • VLSI Architecture For Barrel Distortion Correction In Surveillance Camera Images
    M Mohankumar, R Gowrimanohari, N NITHOSH
    Journal of Electronics and Computer Science 2 (5) , 2015
    2015
    Citations: 5
  • A Novel Design Of Current Mode Multiplier/Divider Circuits For Analog Signal Processing
    M Mohankumar, R Gowrimanohari, MI Niranjana, EA KUMAR
    International Journal of Computer Science and Mobile Computing 3 (10), 918-925 , 2014
    2014
    Citations: 4
  • Secure Network Sharing Nemo based Ad-Hoc
    V Pavithra, M Mohankumar
    In IJCSMC 3 (2), 645-652 , 2014
    2014
    Citations: 4
  • Quantum Key Recovery Attack on Simplified Grain 4-Bit Cipher Using Grover's Algorithm
    M MohanKumar, B Singh, T Thamaraimanalan, SK Korada, P Yuvaraj, ...
    2024 10th International Conference on Advanced Computing and Communication … , 2024
    2024
    Citations: 3
  • High Speed and Lower Hardware Complexity VLSI Architecture for Lifting Based Discrete Wavelet Transform
    K Kokulavani, M Mohankumar
    In IJCSMC 3 (3), 733-739 , 2014
    2014
    Citations: 3
  • Efficient VQE approach for accurate simulations on the Kagome lattice
    S Jyothikamalesh, A Kaarnika, M Mohankumar, S Vishwakarma, ...
    International Conference on Artificial Intelligence and Knowledge Processing … , 2023
    2023
    Citations: 2
  • Multi-Parameter Smart Health Monitoring System Using Arduino-Uno
    M Mohankumar, PB Kirthana, M Shree, M Mylsamy
    Multi-Parameter Smart Health Monitoring System Using Arduino-Uno , 2022
    2022
    Citations: 2
  • Android based smart vehicle tracking system
    D Kousik, C Muniswaran, E Nandhini, X Nelson Britto, KM Mohan
    IJSRCSEIT 2 (2), 215-218 , 2017
    2017
    Citations: 2
  • Machine Learning-Based Analysis of Lifestyle Factors for Sleep Apnea Detection
    M Nandhini, CS Evangeline, MM Kumar, V Sureshkumar
    2025 8th International Conference on Circuit, Power & Computing Technologies … , 2025
    2025
    Citations: 1
  • Experimental Analysis on SVM-based Image Classifiers for Medical Applications
    C Venkataramanan, M Mohankumar, K Mohanapriya, KG Kamalisri, ...
    2023 Second International Conference on Advances in Computational … , 2023
    2023
    Citations: 1
  • Efficient VQE approach for accurate simulations on the Kagome lattice
    S Vishwakarma, S Ganguly
    arXiv preprint arXiv:2306.00467 , 2023
    2023
    Citations: 1
  • A Novel Undistorted Image Fusion and DWT Based Compression Model with FPGA Implementation for Medical Applications
    M Mohankumar, S Akilan, B Hariprasath, R Ariprasath, SD Dharsan
    2022
    Citations: 1
  • Distortion Correction Scheme for Multiresolution Camera Images
    NS M.Mohankumar , T.Thamaraimanalan
    Asian Journal of Applied Science and Technology (AJAST) 1 (1), 195-198 , 2017
    2017
    Citations: 1
  • Efficient Matrix Codes for Error Correction in Memory
    M Mohankumar, T Dhivya
    International Journal of Research in Advent Technology 4 (4), 84-92 , 2016
    2016
    Citations: 1
  • Comparative Analysis on Cold CMOS in Advanced FinFET Technology at 300 K and 77 K
    K Mohanapriya, A Shanmugapriya, M Mohankumar, D Saranyanandhini
    2026 IEEE International Conference on Interdisciplinary Approaches in … , 2026
    2026