G.NagaJyothi
@asst.professor
Asst.Professor and ECE
Madanapalle Institute of Technology and Science
working as Asst. Professor in the ECE department at Madanapalle Institute of Technology and Science. She completed her full-time Ph.D. in VIT in 2020. She has around 16 national and International Scopus and SCI journals.
EDUCATION
Institute of Technology
M.Tech-2008-Vellore Institute of Technology
B.Tech-2006-JNTU-Ananatapore
RESEARCH, TEACHING, or OTHER INTERESTS
Hardware and Architecture, Engineering, Speech and Hearing, Electrical and Electronic Engineering
Scopus Publications
Scholar Citations
Scholar h-index
Scholar i10-index
Scopus Publications
J. Avanija, K. E. N. Kumar, Ch Usha Kumari, G. N. Jyothi, Srujan Raju and Reddy Madhavi
CSIR-National Institute of Science Communication and Policy Research (NIScPR)
The integration of intelligence into everyday products has been possible due to the ongoing shrinking of hardware and a rise in power efficiency. The Internet of Things (IoT) area arose from the tendency to add computational capabilities to so-called non-intelligent daily items. IoT systems are attractive targets for cyber-attacks because they have many applications. Adversaries use a variety of Advanced Persistent Threat (APT) strategies and trace the source of cyber-attack events to safeguard IoT networks. The Particle Deep Framework (PDF), which is proposed in this study, is a novel Network Forensics (NF) that encompasses the digital investigative phases for spotting & tracing attack activity in IoT networks. The suggested framework contains three novel functionalities for dealing with encrypted networks, such as collecting network data flows & confirming their integrity, using a PSO algorithm, "Bot-IoT "& "UNSW NB15" datasets. The suggested PDF is related to several deep-learning methods. Experimental outcomes show that the proposed framework is very good at discovering & tracing cyber-attack occurrences when compared to existing approaches. The proposed design is implemented using neural network technology. The proposed design has 10% accuracy when compared with the existing structure. This paper is expected to offer a quick reference for researchers interested in understanding the use of network
Aliya Thaseen, Raheem Unnisa, Naheed Sultana, K. Reddy Madhavi, Grande. NagaJyothi, and S. Kirubakaran
Springer Nature Singapore
Grande Nagajyothi, G. Pavan Kumar, Budati Suresh Kumar, B. P. Deepak Kumar, and A. K. Damodaram
Springer Nature Singapore
Gunnam Suryanarayana, Vijayakumar Varadarajan, Siva Ramakrishna Pillutla, Grande Nagajyothi, and Ghamya Kotapati
MDPI AG
Existing infrared (IR)-visible (VIS) image fusion algorithms demand source images with the same resolution levels. However, IR images are always available with poor resolution due to hardware limitations and environmental conditions. In this correspondence, we develop a novel image fusion model that brings resolution consistency between IR-VIS source images and generates an accurate high-resolution fused image. We train a single deep convolutional neural network model by considering true degradations in real time and reconstruct IR images. The trained multiple degradation skilled network (MDSNet) increases the prominence of objects in fused images from the IR source image. In addition, we adopt multi-resolution singular value decomposition (MRSVD) to capture maximum information from source images and update IR image coefficients with that of VIS images at the finest level. This ensures uniform contrast along with clear textural information in our results. Experiments demonstrate the efficiency of the proposed method over nine state-of-the-art methods using five image quality assessment metrics.
Avanija J., Suneetha Konduru, Vijetha Kura, Grande NagaJyothi, Bhanu Prakash Dudi, and Mani Naidu S.
IGI Global
Modern power and energy systems are becoming more complicated and uncertain as distributed energy resources (DERs), flexible loads, and other developing technologies become more integrated. This brings great challenges to the operation and control. Furthermore, the deployment of modern sensor and smart metres generates a considerable amount of data, which opens the door to fresh data-driven ways for dealing with complex operation and control difficulties. One of the most commonly touted strategies for control and optimization problems is reinforcement learning (RL). Designing a fuzzy Q-learning power energy system using RL technique will control and reduce the problems arranging in the energy system.
K. M Karthick Raghunath, Manjula Sanjay Koti, R. Sivakami, V. Vinoth Kumar, Grande NagaJyothi, and V. Muthukumaran
Springer Science and Business Media LLC
Grande Naga Jyothi, Kishore Sanapala, and A. Vijayalakshmi
Springer Science and Business Media LLC
Grande NagaJyothi and Sriadibhatla Sridevi
Springer Science and Business Media LLC
Grande Naga Jyothi, Kundu Debanjan, and Gorantla Anusha
Springer Singapore
Grande NagaJyothi and Sriadibhatla Sridevi
Springer Science and Business Media LLC
Grande Naga Jyothi, , Gorantla Anusha, Debanjan Kunda, , and
Blue Eyes Intelligence Engineering and Sciences Engineering and Sciences Publication - BEIESP
Here, we are proposing a novel design of 2:4 decoder and 4:16 decoders which are designed by using line decoder concept. By using proposed design, the area and power consumption of 2:4 decoder and 4:16 decoder can be reduced. In the existing work they have used DVL (Dual Value Logic) and Transmission gate Logic to implement a 14-Transistor 2:4 decoder for minimizing the transistor count. By using 2:4 pre-decoders and post-decoders they implemented 4:16 decoders. Mixed logic is also used for this purpose. Here we have implemented a single 2:4 decoder with minimum transistor count and low power consumption which is used to design a 4:16 decoder. We implement the proposed design in Cadence Virtuoso simulation at 90nm technology and calculated the power and area.
Grande Naga Jyothi and Sridevi Sriadibhatla
Springer Singapore
Debanjan Kundu, Sonali Guin, Grande NagaJyothi, and Sriadibhatla Sridevi
IEEE
The advancement of FinFET based applications are emerging rapidly over the last few years due to its advantages in terms of power and speed over CMOS technology. Current Comparator (CC) find its wide application in the circuits which use Multi-Valued Logic (MVL) along with the analogue circuits and various electronics devices over decades. Mainly in ADC or any sensing devices, the CC finds its application. Exiting model of function generator had been implemented in CMOS 180nm technology. The configuration consists of second generation current conveyor (CCII) as an active device then followed by Schmitt trigger and current mode integrator. In this paper, the logic of Traff comparator has been used to develop the current comparator-based function generator [2] in both CMOS and FinFET technology. Due to FinFET's high speed and low power consumption ability, a noble approach is used by implementing the function generator using FinFET in 30nm technology and the and the output obtained from this system is compared with the outputs of the function generator on CMOS 90nm technology.
R. Sakthivel, Grande Naga Jyothi, and N. Dilip Kumar
ACM
This paper presents about the design of a low power 10-bit 50-M sample /sec Sample and Hold amplifier. A sample and hold amplifier (SHA) acts as a front end block for an Analog Digital Circuit (ADC). To realize a low power SHA, a power efficient Operational Tran-conductance Amplifier (OTA) is to be designed and used. In the literature, many topologies of OTA are proposed for low power. In this paper, an Improved Recycling Folded Cascade (IRFC) OTA existing in the literature is used for realizing SHA and is proposed. In addition to this the SHA includes bottom plate sampling and bootstrap switch to reduce the non-linear distortion. The IRFC OTA used in the design of SHA is implemented using TSMC 90 nm Process. It achieves a DC gain of 73 dB, Unity Gain Bandwidth (UGB) of 70 MHz and with a phase margin of 63 degrees. The proposed SHA is designed and simulated using spectre simulator. From the simulation, it is noted that the SHA achieves a Spurious Free Dynamic Range (SFDR) of 63.44dB and SNDR of 60.6dB for a sampling frequency of 50MS/s with a peak-peak voltage of 1.2 Volts. The S/H circuit consumes 0.44mW of power.
Grande Naga Jyothi and Sriadibhatla Sridevi
American Scientific Publishers
Naga Jyothi Grande and Sriadibhatla Sridevi
IEEE
This paper presents a brief on the implementation of reconfigurable shared LUT (look-up-table) based Distributed Arithmetic (DA) for the higher order finite-impulse response (FIR) filters whose filter coefficients can be changed during run time. In this architecture all the multipliers and adders are replaced by the register banks, multiplexers and the shifters. The throughput rate of the design is increased by having shared LUTs instead of ROM in the DA FIR filter architecture. By implementing this concept in ASIC, the area, area delay product (ADP), minimum cycle period (MCP) and energy per sample are reduced when compare with the conventional DA architecture. The architecture supports 95 MHz sampling frequency.
Grande NagaJyothi and Sriadibhatla SriDevi
IEEE
Finite impulse response (FIR) filter is an influential block in various signal processing applications. The complexities in VLSI implementation of FIR filters is dominated by the number of multiply and accumulate (MAC) operations. Distributed Arithmetic (DA) is an alternative technique where the MAC operations can be replaced by a series of look-up tables and addition operations. FIR filter based on DA are computationally efficient because of high degree of mechanization involved in the implementation of MAC operations using DA. Many reconfigurable and non-reconfigurable FIR filter architectures can be developed using DA. This paper reviews the existing FIR filter architectures based on DA. LUT based DA and LUT-less DA are the significant methods in the implementation of non-reconfigurable filters. This brief summarizes the area and power reports of the existing non-reconfigurable FIR filter architectures based on both LUT based DA and LUT-less DA. One dimensional and two dimensional systolic DA based architectures for FIR filter implementation are also briefed. DA based adaptive FIR techniques are explained. This paper presents the comparative results of FIR and adaptive FIR filter architectures in terms of area, power, area-delay product, minimum cycle period and energy per sample. This survey can form a basis for further research on DA based FIR filter architectures.