Padma Challa received her M.Tech degree in VLSI System Design from JNTUA Ananthapuramu in 2013, and Ph.D in the area of VLSI and Signal Processing from Jawaharlal Nehru Technological University Ananthapuramu (JNTUA) in 2023, and is now currently working as Associate Professor in ECE department at Sri Venkateswara College of Engineering, Tirupati. Her area of interests includes Low Power VLSI Architecures, Signal Processing and IOT. She can be contacted at email: padmasekhar85@
DESIGN AND ANALYSIS OF PARTITION TECHNIQUE BASED DADDAMULTIPLIER ARCHITECTURE D. Kalaiyarasi, T. Suguna, C. Padma, C. Nalini, M. Sundar, et al. Arpn Journal of Engineering and Applied Sciences, 2025 This paper combines two design strategies to speed up column compression multiplication using the Dadda algorithm: decomposing partial products into two sections so that they can be compressed individually in parallel columns and added more quickly using a ripple carry adder and a Binary to Excess-1 converter. This paper also proposes multiplexer based full adder and a half adder designs to optimize power dissipation and propagation delay. The proposed Dadda multiplier of size 8,16,32 and 64 is designed by employing proposed adder designs and is simulated and synthesized using Altera Quartus II with EP2S15F484C3 device for 90nm technology of supply voltage of 1.2V and observed the performance parameters such as delay, power, Maximum Usable Frequency (MUF), Power Delay Product (PDP) and area respectively. It is observed that the proposed partitioned Dadda multiplier in this work,on an average, was able to minimize ALUTs utilization by 73.16%, delay by 51.57%, power by 47.38%, PDP by 73.89% and MUF in an average is increased by 51.57% when compared to existing works. It is concluded that the suggested multiplier can be employed in applications where power and propagation delay are of major concerns since the proposed multiplier design has substantially optimized for all the performance parameters than the conventional Dadda multiplier.
PERFORMANCE OPTIMIZED GROUP DECOMPOSITION DADDA MULTIPLIER FOR DSP APPLICATIONS Arpn Journal of Engineering and Applied Sciences, 2025 This study introduces an extremely fast grouping and decomposition multiplier, providing a novel method of binary multiplication. The suggested multiplier combines the Wallace tree and Dadda multiplier with an innovative grouping and decomposition method such that a total number of partial products and critical path delay are minimized. The full adder used in the proposed multiplier structure is designed by using the GDI technique. The proposed multiplier is implemented using a 45 nm CMOS technology and evaluated against state-of-the-art binary multipliers in terms of speed, power consumption, and area. It is observed from the results that the suggested multiplier has improved performance when compared with existing multipliers. It is concluded that the PDP of the proposed 8-bit Group Decomposition Multiplier (PGDM) with the mentioned multipliers is reduced by 68.11%, 65.63% and 30.72% when compared with the 8-bit Wallace tree, Dadda multiplier and Group Decomposition (GD) multiplier respectively and hence concluded that the proposed multiplier design can be employed in DSP applications for high-speed digital signal processing applications including audio and video processing.
Efficient Approximate Adders for Image Processing Applications C. Padma, Suresh Babu Potladurty, C. Nalini, T. Suguna, CH. Pallavi 2024 International Conference on Advances in Computing Research on Science Engineering and Technology Acroset 2024, 2024 This effort sacrificed accuracy in order to design fast, energy-efficient adders. In order to minimize propagation delay and reduce power consumption, the proposed design truncates half of the adder area. Additionally, internal stage input-output pipelining to the parallel prefix adder can further optimize propagation delay to half of its original value. By significantly raising the approximation adder error, the MSP minimizes the parameters while utilizing the exact calculation and LUTs as resources. In comparison to the current LEADx and APEx, our proposed adder is now efficient in terms of parameters. Xilinx Vivado is used to synthesize the design, simulation, and efficacy of the suggested method. As a case study, the suggested approximation adders are applied in a video encoding application. For video encoding applications, LEADx provided superior quality when compared to other types of approximation adders. Thus, our suggested approximate adders can be useful in efficient FPGA designs of error-tolerant applications.
High Speed Single Precision 64-Tap FIR Filter Using Urdhva Tiryagbhyam Sutra Satyam, Neelima K, M. Sandhiya, C. Padma, Shaik Jaffar Ali, et al. 2024 IEEE Students Conference on Engineering and Systems Interdisciplinary Technologies for Sustainable Future Sces 2024, 2024 In high computing applications like signal and image processing, the computational demand for floating-point multiplication remains paramount. However, the intrinsic complexity of this operation translates into substantial time and power consumption. Addressing this challenge, this paper presents a novel and efficient methodology for IEEE 754 floating-point 64-tap FIR Filter, with a primary emphasis on minimizing both delays in time and area utilization. The Urdhva Tiryagbhyam sutra is used to reduce the delay in multiplication. This paper presents a process to devise filter coefficients and implementation of them for 64-tap 32-bit FIR filter design, which are modeled in Verilog HDL and implemented for XC7K70TFBV676-1 Kintex-7 FPGA board in Xilinx Vivado Tool. The obtained results prove that the proposed FIR filter design proves to be better than the existing FIR filter design as it reduces area by 51.11%, delay by 45.83% and power dissipation by 19.49%. Also the proposed FIR filter design proves to be better than the existing FIR filter design as it reduces Area Delay Product by 73.52% and Power Delay Product by 56.39%.
Implementation of high performance FFT architecture for DSP applications International Journal of Advanced Science and Technology, 2020
RECENT SCHOLAR PUBLICATIONS
Comparative Analysis of 32-bit Carry look ahead Adder using ECRL and PFAL Logic CP SHAIK HIBZA INTERNATIONAL JOURNAL OF CREATIVE RESEARCH THOUGHTS - IJCRT 13 (11), 232-242 , 2025 2025
Implementation of I2C Protocol with Adaptive Baud Rate for N Number of Bits Using VERILOG CP S Aparna 2025 7th International Conference on Control Systems, Mathematical Modeling … , 2025 2025
Hardware Efficient Implementation of Image Enhancement Algorithms Using Xilinx System Generator PC Neelima Koppala, P. Rajyalakshmi, Attar Farooq Hussain, Suguna Tangimi ... 2025 International Conference on Intelligent Communication Networks and … , 2025 2025
An Efficient 32-Bit Carry Look Ahead Adder using PFAL for Low Power Circuits. CP Shaik Hibza 2025 Global Conference on Information Technology and Communication Networks … , 2025 2025
Adept Domino Logic for Modified Schmitt Trigger Circuits K Neelima, K Maheswari, SS Vali, CH Pallavi, C Padma, JA Shaik 2025 International Conference on Computing, Intelligence, and Application … , 2025 2025
DESIGN AND ANALYSIS OF PARTITION TECHNIQUE BASED DADDAMULTIPLIER ARCHITECTURE D Kalaiyarasi, T Suguna, C Padma, C Nalini, MS Raj, G Nagarajan 2025
PERFORMANCE OPTIMIZED GROUP DECOMPOSITION DADDA MULTIPLIER FOR DSP APPLICATIONS PVKKVLK Suguna T. , Kalaiyarasi D. , C. Padma , R. Kiran Kumar 2025
Post-Pandemic Economy–Shocks, Risks and Suggestive Measures K Neelima, CH Kavya, C Padma, T Suguna Economic Uncertainty in the Post-Pandemic Era, 187-197 , 2024 2024 Citations: 1
Design of a 64-bit SQRT-CSLA with reduced area and high-speed applications in low power VLSI circuits CH Pallavi, C Padma, RK Kumar, T Suguna, C Nalini arXiv preprint arXiv:2410.15736 , 2024 2024 Citations: 1
Improved Domino Logic based Low Power CMOS Schmitt Trigger Circuit at Nano Scale Regime P Challa, C Nalini, S Tangimi, N Koppala Journal of Advanced Research in Applied Sciences and Engineering Technology … , 2024 2024
Efficient approximate adders for image processing applications C Padma, SB Potladurty, C Nalini, T Suguna, CH Pallavi 2024 International Conference on Advances in Computing Research on Science … , 2024 2024 Citations: 4
High Speed Single Precision 64-Tap FIR Filter Using Urdhva Tiryagbhyam Sutra K Neelima, M Sandhiya, C Padma, SJ Ali, KR Meruva 2024 IEEE Students Conference on Engineering and Systems (SCES), 1-5 , 2024 2024 Citations: 1
Post-Pandemic Biometric Challenges and Solutions: A Shocker to Supply Chain K Neelima, B Madhavi, C Padma, BK Pandey, G Gowwrii, SS Manaktala AI and Machine Learning Impacts in Intelligent Supply Chain, 196-208 , 2024 2024 Citations: 4
Hybrid Cryptography and Steganography-Based Security System for IoT Networks T Suguna, C Padma, MJ Rani, GP Priya International journal on recent innovation trends in computing and … , 2023 2023 Citations: 2
FIR filter design using urdhva triyagbhyam based on truncated wallace and dadda multiplier as basic multiplication unit K Neelima, C Padma, C Nalini, M Balaji 2023 IEEE 12th International Conference on Communication Systems and Network … , 2023 2023 Citations: 13
A Novel Approach for the Analysis on Classification of ILDs Using HRCT Images K Praveena, C Nalini, C Padma International Conference on Intelligent Healthcare and Computational Neural … , 2022 2022
Efficient cached 64 point FFT processor using floating point arithmetic for OFDM application C Padma, P Jagadamba, RR Patil Instrumentation, Mesure, Metrologie 21 (1), 21 , 2022 2022 Citations: 3
Design of FFT processor using low power Vedic multiplier for wireless communication C Padma, P Jagadamba, PR Reddy Computers & Electrical Engineering 92, 107178 , 2021 2021 Citations: 17
Energy Efficient Floating Point Fft/Ifft Processor For Mimo-Ofdm Applications C Padma Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12 (10 … , 2021 2021
Implementation of High Performance FFT Architecture for DSP Applications C.Padma, P.Jagadamba, P. Ramana Reddy International journal of Advanced Science and Technology (IJAST) 29 (No.3 … , 2020 2020 Citations: 3
MOST CITED SCHOLAR PUBLICATIONS
Design of FFT processor using low power Vedic multiplier for wireless communication C Padma, P Jagadamba, PR Reddy Computers & Electrical Engineering 92, 107178 , 2021 2021 Citations: 17
FIR filter design using urdhva triyagbhyam based on truncated wallace and dadda multiplier as basic multiplication unit K Neelima, C Padma, C Nalini, M Balaji 2023 IEEE 12th International Conference on Communication Systems and Network … , 2023 2023 Citations: 13
Smart Traffic Control System for Emergency Vehicle Clearance CP D. Aswani International Journal and Magazine of Engineering Technology Management and … , 2016 2016 Citations: 8
Efficient approximate adders for image processing applications C Padma, SB Potladurty, C Nalini, T Suguna, CH Pallavi 2024 International Conference on Advances in Computing Research on Science … , 2024 2024 Citations: 4
Post-Pandemic Biometric Challenges and Solutions: A Shocker to Supply Chain K Neelima, B Madhavi, C Padma, BK Pandey, G Gowwrii, SS Manaktala AI and Machine Learning Impacts in Intelligent Supply Chain, 196-208 , 2024 2024 Citations: 4
Efficient cached 64 point FFT processor using floating point arithmetic for OFDM application C Padma, P Jagadamba, RR Patil Instrumentation, Mesure, Metrologie 21 (1), 21 , 2022 2022 Citations: 3
Implementation of High Performance FFT Architecture for DSP Applications C.Padma, P.Jagadamba, P. Ramana Reddy International journal of Advanced Science and Technology (IJAST) 29 (No.3 … , 2020 2020 Citations: 3
Hybrid Cryptography and Steganography-Based Security System for IoT Networks T Suguna, C Padma, MJ Rani, GP Priya International journal on recent innovation trends in computing and … , 2023 2023 Citations: 2
A Review on Optimized FFT Architectures for Wireless Communication System C.Padma, P.Jagadamba, P. Ramana Reddy Journal of Advanced Research and Dynamical and Control Systems 10 (14), 1654 … , 2018 2018 Citations: 2
Smart agriculture seeding and fertilizer spray robot using IoT B Kumar, C Padma Int J Sci Eng Technol Res 6 (03), 0437-0440 , 2017 2017 Citations: 2
Post-Pandemic Economy–Shocks, Risks and Suggestive Measures K Neelima, CH Kavya, C Padma, T Suguna Economic Uncertainty in the Post-Pandemic Era, 187-197 , 2024 2024 Citations: 1
Design of a 64-bit SQRT-CSLA with reduced area and high-speed applications in low power VLSI circuits CH Pallavi, C Padma, RK Kumar, T Suguna, C Nalini arXiv preprint arXiv:2410.15736 , 2024 2024 Citations: 1
High Speed Single Precision 64-Tap FIR Filter Using Urdhva Tiryagbhyam Sutra K Neelima, M Sandhiya, C Padma, SJ Ali, KR Meruva 2024 IEEE Students Conference on Engineering and Systems (SCES), 1-5 , 2024 2024 Citations: 1
A Novel Approach for Design & Implementation of Traffic Light Controller System Using FPGA C Padma, C Pallavi International Journal for Innovative Engineering & Management Research 7 (12) , 2018 2018 Citations: 1
Comparative Analysis of 32-bit Carry look ahead Adder using ECRL and PFAL Logic CP SHAIK HIBZA INTERNATIONAL JOURNAL OF CREATIVE RESEARCH THOUGHTS - IJCRT 13 (11), 232-242 , 2025 2025
Implementation of I2C Protocol with Adaptive Baud Rate for N Number of Bits Using VERILOG CP S Aparna 2025 7th International Conference on Control Systems, Mathematical Modeling … , 2025 2025
Hardware Efficient Implementation of Image Enhancement Algorithms Using Xilinx System Generator PC Neelima Koppala, P. Rajyalakshmi, Attar Farooq Hussain, Suguna Tangimi ... 2025 International Conference on Intelligent Communication Networks and … , 2025 2025
An Efficient 32-Bit Carry Look Ahead Adder using PFAL for Low Power Circuits. CP Shaik Hibza 2025 Global Conference on Information Technology and Communication Networks … , 2025 2025
Adept Domino Logic for Modified Schmitt Trigger Circuits K Neelima, K Maheswari, SS Vali, CH Pallavi, C Padma, JA Shaik 2025 International Conference on Computing, Intelligence, and Application … , 2025 2025
DESIGN AND ANALYSIS OF PARTITION TECHNIQUE BASED DADDAMULTIPLIER ARCHITECTURE D Kalaiyarasi, T Suguna, C Padma, C Nalini, MS Raj, G Nagarajan 2025
