PANKAJ KUMAR SHARMA
@nitsri.ac.in
Assistant Professor (Contract), Electronics & Communication Engineering
NIT Srinagar
RESEARCH, TEACHING, or OTHER INTERESTS
Electrical and Electronic Engineering
Scopus Publications
Scholar Citations
Scholar h-index
Scholar i10-index
Scopus Publications
Pankaj Kumar Sharma, Sadaf Tasneem, and Rajeev Kumar Ranjan
Institute of Electrical and Electronics Engineers (IEEE)
In this article, we have proposed an electronic tunable grounded meminductor emulator (MIE) using a single voltage difference transconductance amplifier (VDTA). Along with one VDTA, two MOSFETs and two capacitors are used in the proposed MIE. Overall, the proposed MIE requires only 18 MOS transistors and two grounded capacitors. The performance of the proposed MIE was validated using Cadence Virtuoso with a 180-nm CMOS library. The layout area of the emulator is only 1081 $\\mu \\text{m}^{2}$ . The proposed design operates up to 25 MHz. To validate the theoretical and simulation results, an experiment was performed using CA3080 ICs and experimental results validate the simulated result. The power consumption of the proposed design is 5.93 mW.
Sadaf Tasneem, Pankaj Kumar Sharma, Rajeev Kumar Ranjan, and Fabian Khateb
MDPI AG
In recent times, much-coveted memristor emulators have found their use in a variety of applications such as neuromorphic computing, analog computations, signal processing, etc. Thus, a 100 MHz flux-controlled memristor emulator is proposed in this research brief. The proposed memristor emulator is designed using a single differential voltage current conveyor (DVCC), three PMOS transistors, and one capacitor. Among three PMOS transistors, two transistors are used to implement an active resistor, and one transistor is used as the multiplier required for the necessary memristive behaviors. Through simple adjustment of the switch, the proposed emulator can be operated in incremental as well as decremental configurations. The simulations are performed using a 180 nm technology node to validate the proposed design and are experimentally verified using AD844AN and CD4007 ICs. The memristor states of the proposed emulator are perfectly retained even in the absence of external stimuli, thereby ascertaining the non-volatility behavior. The robustness of the design is further analyzed using the PVT and Monte Carlo simulations, which suggest that the circuit operation is not hindered by the mismatch and process variations. A simple neuromorphic adaptive learning circuit based on the proposed memristor is also designed as an application.
Pankaj Kumar Sharma, Sagar Surendra Prasad, Sadaf Tasneem, Bindu Priyadarshini, and Rajeev Kumar Ranjan
Elsevier BV
Sagar Surendra Prasad, Prashant Kumar, Niranjan Raj, Pankaj Kumar Sharma, Bindu Priyadarshini, Rajeev Kumar Ranjan, and Pipat Prommee
Elsevier BV
Pankaj Kumar Sharma, Prashant Kumar, and Rajeev Kumar Ranjan
IEEE
In this article, we have proposed a grounded memristor emulator model using CCII and VDIBA blocks. The proposed circuit also uses one resistor and one capacitor along with analog building blocks. The presented memristor emulator operates up to 25 MHz. The proposed memristor is simulated using Cadence Virtuoso 180 nm CMOS parameter. The proposed memristor works at ± 0.9 V and the power consumption is 2.4 mW. The adaptability of the memristor emulator during circuit implementation is tested by connecting the memristors in parallel.
Pankaj Kumar Sharma, Sagar Surendra Prasad, Sadaf Tasneem, and Rajeev Kumar Ranjan
IEEE
In this article, we have proposed an emulator using DVCC and OTA analog building blocks to emulate memristive behavior. Along with OTA and DVCC, one resistor and one capacitor are used in the memristor emulator. The presented memristor emulator works in incremental and decremental mode and operates up to 8 MHz. The proposed memristor emulator is simulated using PSpice with a 180 nm CMOS parameter. The flexibility of the memristor is tested by simulating it at different temperatures. The adaptability of the memristor emulator during circuit implementation is tested by connecting the memristors in parallel.
Sagar Surendra Prasad, Niranjan Raj, Pankaj Kumar Sharma, and Rajeev Kumar Ranjan
IEEE
This research article exhibits grounded memristor emulator circuit. It includes a single Differential Voltage Current Conveyor Transconductance Amplifier (DVCCTA) as an active block with few grounded passive components. The incremental and decremental configurations for the proposed memristor can be achieved through a simple flip of the input ports. The proposed model also provides a resistor-based controllability feature. The workability of the proposed memristor has been demonstrated using PSPICE simulation with CMOS 0.18 μm TSMC technology parameter. The operating frequency and tunability responses in the current-voltage (I-V) plane have been verified in the simulation section and can operate in the megahertz range, showing acceptable accord with the theory. Furthermore, Monte Carlo process analysis, as well as the single and parallel-connected structure, have been analyzed to examine the robustness of the proposed ME model. The proposed emulator circuit is grounded, straightforward and prohibits the use of extra sub-circuit elements making it suitable for integrated circuits implementation.
Pankaj Kumar Sharma, Rajeev Kumar Ranjan, Fabian Khateb, and Montree Kumngern
Institute of Electrical and Electronics Engineers (IEEE)
This article proposes a charged controlled emulator model for memristor and memcapacitor using second-generation Current Conveyor (CCIIs) and Analog Multiplier (AM). The grounded and floating mem-element circuits have been designed using two CCIIs and one multiplier in addition to some passive components. The grounded type of design requires three resistors and three capacitors while floating design necessitates only two resistors and two capacitors. With the help of a switch, the proposed design can be easily switched into a memristor or memcapacitor. The proposed emulator model has been theoretically analyzed and simulated in PSpice to substantiate the effectiveness and accuracy. The practicability of the circuit has been established using commercially available ICs AD844AN and AD633JN. Non-linear characteristics of the proposed memristor emulator have been used to design a chaotic system.
Rajeev Kumar Ranjan, Pankaj Kumar Sharma, Sagar, Niranjan Raj, Bharti Kumari, and Fabian Khateb
World Scientific Pub Co Pte Lt
A charge-controlled memristor emulator circuit based on one kind of active device [operational transconductance amplifier (OTA)] using CMOS technology is introduced in this paper. The proposed circuit can be configured in both incremental and decremental types by using a simple switch. The memristor behavior can be electronically tuned by adjusting the transconductance of the OTAs. By changing the value of the capacitor, the pinched hysteresis loop observed in the current versus voltage plane can be held at higher frequencies. The proposed emulator circuit functions well up to 500 kHz. The experiment has been performed using commercially available OTA ICs (CA3080). The experimental demonstration has been carried out for 10, 20 and 120[Formula: see text]kHz. A simple high-pass filter is explained in both configurations to demonstrate the functionality of the proposed memristor emulator. The proposed circuit has been simulated in PSPICE using 0.5-[Formula: see text]m CMOS parameter. The simulated and experimental results validate the theoretical proposition.