Karim M. Abozeid

@assistant lecturer

Faculty of Engineering
The British University in Egypt



                 

https://researchid.co/karimabozeid

Karim AboZeid received his Master of Science in Electronics and Electrical Communications Engineering from "Cairo University" in 2015. His thesis titled "Ultra Low Power Analog to Digital Converter Using Successive Approximation Register Logic with Voltage Offset Cancellation Technique". He received his Bachelor of Science in Electronics and Electrical Communications Engineering from "Cairo University" in 2009, with a general grade of " Very Good". His graduation project titled "Handoff Algorithm using Neural Networks in Terrestrial HAPS Cellular Systems" received the grade " Excellent". He currently works as an assistant lecturer in Electrical Engineering Department, Faculty of Engineering in The British University in Egypt.
- Certified peer reviewer from Elsevier Researcher Academy.
- Research fields of interest are: Analog Electronics, Digital Electronics, VLSI and Data Converters.

EDUCATION

- Master of Science in Electronics and Electrical Communications Engineering from Cairo University.
- Bachelor of Science in Electronics and Electrical Communications Engineering from Cairo University.

RESEARCH, TEACHING, or OTHER INTERESTS

Computer Engineering, Electrical and Electronic Engineering, Control and Systems Engineering

2

Scopus Publications

6

Scholar Citations

1

Scholar h-index

Scopus Publications

  • 8-bit 22nW SAR ADC using output offset cancellation technique
    Karim M. Abozeid, Mohamed M. Aboudina, and A.H. Khalil
    IEEE
    In this paper we present an offset cancellation technique for a comparator used in SAR (successive approximation register) analog to digital converter improving the signal to noise ratio of the whole system with minimum power consumption at the expense of complexity of the system. An 8-bit SAR ADC is presented with power consumption 22nW, ENOB = 7.051 and SNR = 47.11 dB. All simulations are done under clock frequency = 100 kHz and a supply voltage 1V.

  • Different configurations for dynamic latched comparators used in ultra low power Analog to Digital converters
    Karim M. Abozeid, Mohamed M. Aboudina, and A.H. Khalil
    IEEE
    This paper presents a comparison in the consumed power between different configurations of dynamic latched comparator used in low power Analog to Digital (A/D) converters especially the successive approximation register (SAR) which is used in many Electrical, Radio-frequency identification (RFID) and biomedical applications. This comparison is in architecture, consumed power and propagation time delay. The comparison is done under constant input referred offset.

RECENT SCHOLAR PUBLICATIONS

  • 8-bit 22nW SAR ADC using output offset cancellation technique
    KM Abozeid, MM Aboudina, AH Khalil
    2015 11th International Computer Engineering Conference (ICENCO), 76-79 2015

  • Different configurations for dynamic latched comparators used in ultra low power Analog to Digital converters
    KM Abozeid, MM Aboudina, AH Khalil
    2014 International Conference on Engineering and Technology (ICET), 1-6 2014

  • Variation in Power Consumption with Frequency and Voltage Supply for Different Configurations of Successive Approximation Register Logic
    KM Abozeid, MM Aboudina, AH Khalil
    International Conference (ICNBS 2013) in Nanotechnology, Biotechnology 2013

MOST CITED SCHOLAR PUBLICATIONS

  • Different configurations for dynamic latched comparators used in ultra low power Analog to Digital converters
    KM Abozeid, MM Aboudina, AH Khalil
    2014 International Conference on Engineering and Technology (ICET), 1-6 2014
    Citations: 6