Devalraju Prasad

@sietk.org

Associate Professor and Department of Electrical and Electronics Engineering
Siddharth Institute of Engineering and Technology, Puttur

Devalraju Prasad


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https://researchid.co/devalrajuprasad
9

Scopus Publications

418

Scholar Citations

7

Scholar h-index

7

Scholar i10-index

Scopus Publications

  • A New 29-Level Switched-Diode Multilevel Inverter with Optimal Device Count
    C. Dhanamjayulu, P. Sanjeevikumar, Devalraju Prasad, Shaik Reddi Khasim, Frede Blaabjerg, et al.
    IETE Journal of Research, 2024
  • Solar PV integrated dynamic voltage restorer for enhancing the power quality under distorted grid conditions
    Devalraju Prasad, C. Dhanamjayulu
    Electric Power Systems Research, 2022
  • Solar PV-Fed Multilevel Inverter with Series Compensator for Power Quality Improvement in Grid-Connected Systems
    Devalraju Prasad, Dhanamjayulu C.
    IEEE Access, 2022
    Power quality difficulties arise as a result of Renewable Energy Sources (RES) integrating with the grid. Voltage swell, sag, and harmonic distortion occur on the grid due to power quality issues, which have an impact on customers. An inexpensive series compensator, like the Dynamic Voltage Restorer (DVR), is the best solution for overcoming the aforementioned problems. In this article, a solar PV integrated DVR with a novel multilevel inverter is introduced to address the power quality issues in the grid. The main objective of the proposed work is to develop a DVR integrated with a 23-level multilevel inverter to enhance the power quality. In addition, an improved INC-MPPT technique is designed for the boost converter for maximum energy extraction from the solar PV modules. Despite numerous benefits of multilevel inverters, there exist several reliability challenges such as fewer component counts and reduced THD. The suggested topology can able to generate 23 levels of output voltage with asymmetrical DC sources. The MLI has several advantages such as a reduction in the overall component count, cost and size of the inverter. Additionally, a detailed mathematical analysis is presented for the rotating dq reference frame control. The dynamic performance of the DVR is evaluated with a balanced load and implemented experimentally. Simulation results of the proposed system are carried out using MATLAB/Simulink. The proposed system is implemented using a dSPACE controller with a laboratory hardware prototype and OPAL-RT real-time simulator setup as well. The results show that the design of the proposed system is more effective at compensating for voltage sag and improves the power quality significantly. The THD obtained at the grid side is lower, which is under IEEE standards.
  • Reduced Voltage Stress Asymmetrical Multilevel Inverter With Optimal Components
    Devalraju Prasad, C. Dhanamjayulu
    IEEE Access, 2022
    The article presents a single phase asymmetrical multilevel inverter with a reduced components and low voltage stress which reduces the size and cost of the system. The structure provides a maximum output voltage of 23 levels with asymmetrical DC sources. There exists several reliability issues in lowering the total harmonic distortion (THD) by utilizing higher components in the design of MLI despite of its merits. Achieving reliability and lowering the THD is a challenging task for the researchers. The proposed 23-level MLI has been investigated with various performance parameters like total voltage standing (TSV), cost function (CF), power loss and efficiency analysis. The suggested MLI is compared with the existing topologies in the recent past and found that it has less voltage stress across the switches and cost-effective. The TSV calculations show that the proposed structure is more efficient in reducing the losses and increasing the efficiency. Hence, based on the evaluations and the comparisons made with the other topologies, it is found that the proposed MLI is well suited for the medium power applications such as FACTS, SVC, DSTATCOM and DVR. As the proposed architecture provides the 23 level output voltage values with asymmetrical DC sources, the configuration can be utilized for improving power quality in grid-connected renewable energy sources. The topology provides a less THD value which is under IEEE standards. The proposed architecture has been designed in MATLAB/Simulink and is implemented experimentally in hardware prototype in the laboratory environment.
  • A Review of Control Techniques and Energy Storage for Inverter-Based Dynamic Voltage Restorer in Grid-Integrated Renewable Sources
    Devalraju Prasad, C. Dhanamjayulu
    Mathematical Problems in Engineering, 2022
    Power quality (PQ) is a key issue, particularly for technologically advanced process equipment, whose performance mainly depends on the quality of supply. Problems with PQ such as voltage swells/sags, interruptions, and harmonics are defined by any voltage, current, or frequency abnormalities causing damage or failure of the end-user equipment. Outages and interruptions lead to malfunctioning of end-user equipment or sensitive loads, such as diagnostic equipment in healthcare facilities, clinics, educational institutions, and detention centers, while further increasing significant economic losses. Custom power devices (CPDs) are recommended for enhancing power quality, and the best and most economical solution is considered to be the dynamic voltage restorer (DVR). Several methods are suggested to improve the PQ by using the dynamic voltage restorer; among them, most encouraging ways are to use a multilevel inverter (MLI) in the dynamic voltage restorer. This article combines the latest work of the literature, as well as a detailed discussion on PQ issues of the grid-integrated renewable energy sources (RESs), DVR principle with its operating procedures, system components, energy storage-based DVR topologies, DVR control unit, and DVR power converter-based topologies. In addition, synthesis of energy storage, control strategies, and multilevel inverters for DVR. This review benefits those interested in investigating DVR as a relevant and comprehensive reference.
  • Correction: Design and Implementation of Seventeen Level Inverter With Reduced Components (IEEE Access (2021) 9 (16746-16760) DOI: 10.1109/ACCESS.2021.3054001)
    C. Dhanamjayulu, Devalraju Prasad, Sanjeevikumar Padmanaban, Pandav Kiran Maroti, Jens Bo Holm-Nielsen, et al.
    IEEE Access, 2022
  • A Novel 19-level Asymmetrical Multilevel Inverter for Dynamic Voltage Restorer Applications
    Prasad Devalraju, Dhanamjayulu C
    3rd IEEE International Virtual Conference on Innovations in Power and Advanced Computing Technologies I Pact 2021, 2021
    A novel 19-level single-phase asymmetrical multilevel inverter with a reduced component topology is presented and to be designed. The designed structure proposed by the topology produces a maximum of 19 levels of output voltage with asymmetrical DC sources without H-bridge and can be used in DVR to improve power quality in the grid-connected renewable sources. This topology reduces the total number of components, cost, and system size. Instead of the multiple benefits of MLI, the presence of a higher component count to reduce THD makes reliability problems. The reliability with less THD is a critical challenge for researchers. Several parameters such as cost function (CF), total voltage standing (TSV), and power loss are analyzed for 19-level MLIs. A cost function is calculated from the total standing voltage, the proposed MLI is compared with several recently published topologies that are cost-effective. A thorough comparison with the graphic representation is carried out of several parameters. The MLI proposed is less compatible with the TSV and components requirement. The total harmonic distortion (THD) obtained is in accordance with the standards of IEEE. The topology is simulated using MATLAB/Simulink.
  • Design and Implementation of 31-Level Asymmetrical Inverter with Reduced Components
    Devalraju Prasad, C. Dhanamjayulu, Sanjeevikumar Padmanaban, Jens Bo Holm-Nielsen, Frede Blaabjerg, et al.
    IEEE Access, 2021
    This paper presents a novel topology for the single-phase 31-level asymmetrical multilevel inverter accomplished with reduced components count. The proposed topology generates maximum 31-level output voltage with asymmetric DC sources with an H-bridge. The fundamental 13-level multilevel inverter (MLI) topology is realized, and further, the topology is developed for 31-level can be used for renewable energy applications. This reduces the overall components count, cost and size of the system. Rather than the many advantages of MLIs, reliability issues play a significant role due to higher components count to reduce THD. This is a vital challenge for the researchers to increase the reliability with less THD. Several parameters are analyzed for both fundamental 13-level and developed 31-level MLIs such as total standing voltage (TSV), cost function (CF) and power loss. The inverter is tested experimentally with various combinational loads and under dynamic load variations with sudden load disturbances. Total standing voltage with the cost function for the proposed MLI is compared with various topologies published recently and is cost-effective. A detailed comparison of several parameters with graphical representation is made. Less TSV and components requirement is observed for the proposed MLI. The obtained total harmonic distortion (THD) is under IEEE standards. The topology is simulated in MATLAB/Simulink and verified experimentally with a hardware prototype under various conditions.
  • Design and Implementation of Seventeen Level Inverter with Reduced Components
    C. Dhanamjayulu, Devalraju Prasad, Sanjeevikumar Padmanaban, Pandav Kiran Maroti, Jens Bo Holm-Nielsen, et al.
    IEEE Access, 2021
    The multilevel inverters (MLI) are resourceful in producing a voltage waveform with superior-quality staircase counterfeit sinusoidal and depressed harmonic distortion (THD). Several conventional topologies are proposed to realize the MLI however, the limitations of these topologies may involve more DC sources and power-switching devices, and less THD, which in turn, increases the cost and size of the inverter. These drawbacks can be eliminated with the proposed hybrid Cascaded H-Bridge Multilevel Inverter with reduced components topology. As compared with the established MLI topologies the recommended topology having a reduced number of DC sources, power-switching devices, component count level factor, lesser TSV, more efficient, lesser THD, and cost-effective. The proposed MLI is a blend of a single-phase T-Type inverter and an H-Bridge module made of sub switches. This article incorporates the design and simulation of the multilevel inverter with staircase PWM technique. Further, the 9-level and 17-level MLI is examined with different combinational loads. The proposed inverter is stable during nonlinear loads, and it is well suited for FACTS and renewable energy grid-connected applications. An operational guideline has been explained with correct figures and tables. The Output voltage wave is realized in numerical simulation. Finally, the experimental demonstrations were performed by implementing a hardware prototype setup for both linear and nonlinear loads using the dSPACE controller laboratory.

RECENT SCHOLAR PUBLICATIONS

  • A new 29-level switched-diode multilevel inverter with optimal device count
    C Dhanamjayulu, P Sanjeevikumar, D Prasad, SR Khasim, F Blaabjerg
    IETE Journal of Research 70 (3), 2989-3004 , 2024
    2024.0
    Citations: 4
  • Solar PV integrated dynamic voltage restorer for enhancing the power quality under distorted grid conditions
    D Prasad, C Dhanamjayulu
    Electric Power Systems Research 213, 108746 , 2022
    2022.0
    Citations: 53
  • Solar PV-fed multilevel inverter with series compensator for power quality improvement in grid-connected systems
    D Prasad, C Dhanamjayulu
    IEEE Access 10, 81203-81219 , 2022
    2022.0
    Citations: 67
  • Reduced voltage stress asymmetrical multilevel inverter with optimal components
    D Prasad, C Dhanamjayulu
    IEEE Access 10, 53546-53559 , 2022
    2022.0
    Citations: 31
  • A Review of Control Techniques and Energy Storage for Inverter‐Based Dynamic Voltage Restorer in Grid‐Integrated Renewable Sources
    D Prasad, C Dhanamjayulu
    Mathematical Problems in Engineering 2022 (1), 6389132 , 2022
    2022.0
    Citations: 21
  • A novel 19-level asymmetrical multilevel inverter for dynamic voltage restorer applications
    P Devalraju, C Dhanamjayulu
    2021 Innovations in Power and Advanced Computing Technologies (i-PACT), 1-7 , 2021
    2021.0
    Citations: 18
  • Design and implementation of 31-level asymmetrical inverter with reduced components
    D Prasad, C Dhanamjayulu, S Padmanaban, JB Holm-Nielsen, ...
    IEEe Access 9, 22788-22803 , 2021
    2021.0
    Citations: 71
  • Design and implementation of seventeen level inverter with reduced components
    C Dhanamjayulu, D Prasad, S Padmanaban, PK Maroti, JB Holm-Nielsen, ...
    IEEE access 9, 16746-16760 , 2021
    2021.0
    Citations: 153
  • A Novel Control Strategy for Achieving Power Quality in the Grid Interconnection of Distributed Generation
    D PRASAD, GVS BABU
    2014.0
  • A New Approach LVRT Control with Enhanced Reactive Power Support for DFIG Wind Turbines
    D Prasad, J Balaji, NS Rao

MOST CITED SCHOLAR PUBLICATIONS

  • Design and implementation of seventeen level inverter with reduced components
    C Dhanamjayulu, D Prasad, S Padmanaban, PK Maroti, JB Holm-Nielsen, ...
    IEEE access 9, 16746-16760 , 2021
    2021.0
    Citations: 153
  • Design and implementation of 31-level asymmetrical inverter with reduced components
    D Prasad, C Dhanamjayulu, S Padmanaban, JB Holm-Nielsen, ...
    IEEe Access 9, 22788-22803 , 2021
    2021.0
    Citations: 71
  • Solar PV-fed multilevel inverter with series compensator for power quality improvement in grid-connected systems
    D Prasad, C Dhanamjayulu
    IEEE Access 10, 81203-81219 , 2022
    2022.0
    Citations: 67
  • Solar PV integrated dynamic voltage restorer for enhancing the power quality under distorted grid conditions
    D Prasad, C Dhanamjayulu
    Electric Power Systems Research 213, 108746 , 2022
    2022.0
    Citations: 53
  • Reduced voltage stress asymmetrical multilevel inverter with optimal components
    D Prasad, C Dhanamjayulu
    IEEE Access 10, 53546-53559 , 2022
    2022.0
    Citations: 31
  • A Review of Control Techniques and Energy Storage for Inverter‐Based Dynamic Voltage Restorer in Grid‐Integrated Renewable Sources
    D Prasad, C Dhanamjayulu
    Mathematical Problems in Engineering 2022 (1), 6389132 , 2022
    2022.0
    Citations: 21
  • A novel 19-level asymmetrical multilevel inverter for dynamic voltage restorer applications
    P Devalraju, C Dhanamjayulu
    2021 Innovations in Power and Advanced Computing Technologies (i-PACT), 1-7 , 2021
    2021.0
    Citations: 18
  • A new 29-level switched-diode multilevel inverter with optimal device count
    C Dhanamjayulu, P Sanjeevikumar, D Prasad, SR Khasim, F Blaabjerg
    IETE Journal of Research 70 (3), 2989-3004 , 2024
    2024.0
    Citations: 4
  • A Novel Control Strategy for Achieving Power Quality in the Grid Interconnection of Distributed Generation
    D PRASAD, GVS BABU
    2014.0
  • A New Approach LVRT Control with Enhanced Reactive Power Support for DFIG Wind Turbines
    D Prasad, J Balaji, NS Rao