Dr. Vasudeva Bevara

@gmrit.edu.in

Sr. Assistant Professor, ECE Department, GMRIT
Sr. Assistant Professor, GMRIT

Dr. Vasudeva Bevara


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https://researchid.co/bevaravasudeva

RESEARCH, TEACHING, or OTHER INTERESTS

Electrical and Electronic Engineering
12

Scopus Publications

67

Scholar Citations

6

Scholar h-index

1

Scholar i10-index

Scopus Publications

  • An ultra-low power QCA based vedic multiplier for digital radar application
    Rajender Daggula, Vasudeva Bevara
    E Prime Advances in Electrical Engineering Electronics and Energy, 2024
    Quantum-dot cellular automata (QCA) is a promising nanotechnology that appears to meet the requirements of high speed radar applications. Due to its advantages, including its extremely low power dissipation and less occupied area, it is highly regarded. The multiplier module is an essential component in Phased Array Radar (PAR). In the real-time PAR based systems, many applications like digital beam forming, local oscillators, and communication receivers etc. requires multiplication operation. However, the most important factors in these systems are the area and power consumption. This paper presents an ultra-low power vedic multiplier using QCA technology, and it provides the effective clocking, reduce the number of cells, and low energy dissipation. The 4×4 vedic multiplier utilizes only 2940 cells and occupies 7.33μm2 area with 7.64×10−1eV of energy dissipation. The total consumed power of this module is 1.61nW. This architecture outperforms complementary metal-oxide-semiconductor (CMOS) based circuits in terms of power by 90%. The proposed contribution will initiate a new direction of research into real-time PAR based systems.
  • Ultra low power reversible arithmetic processor based on QCA
    Vasudeva Bevara, Srinu Bevara, Sudhakar Busi, R. V. V. Murali Krishna, PramodKumar Aylapogu
    Optical and Quantum Electronics, 2024
  • Optimizing the Threshold Modified Comparator Circuit (TMCC) with NCFET Technology for Low Power and High-Speed Performance
    Venu Siripurapu, Thota Durga Prasad, Sailada Srivallika, Vasudeva Bevara, Sarvisetti Soma Surya
    Proceedings 2024 IEEE 16th International Conference on Communication Systems and Network Technologies Cicn 2024, 2024
    Comparators had been a major part in the design of various applications like ADCs, Relaxations Oscillators, Schmitt trigger, and many more. The design of these comparators have been advancing over the passing years. the main parameters considered while designing of the comparator are area, power consumed, delay in comparing and giving us the output. we have designed a TMCC (Threshold modified comparator circuit) using NCFET (Negative capacitance field effect transistor) and its power consumption, area utilization and delay have been calculated. The proposed TMCC using NCFET technology have been designed using 40 nm technology. It consumes an average power of 3.5 pW and the delay is 1.325 ns. The above-mentioned parameters have been reduced to a major amount by using NCFET while compared to the CMOS technology.
  • Design of an efficient QCA-based median filter with energy dissipation analysis
    Vasudeva Bevara, Syed Alihussain, P. N. S. B. S. V. Prasad, Pradyut K. Sanki
    Journal of Supercomputing, 2023
  • RF choke based methodology for flange effect mitigation and antenna isolation improvement in bistatic radars of aerospace vehicles
    Rajender Daggula, Vasudeva Bevara, Manisha Kamal K., Samba Siva Rao Kumbha, Amit Acharyya
    AEU International Journal of Electronics and Communications, 2023
  • High performance 2n:1:2n reversible MUX/DMUX architecture for quantum dot cellular automata
    Vasudeva Bevara, Shakamuri Narendra Chowdary, Bolem Venkata Surendra Babu, Pradyut Kumar Sanki
    International Journal of Numerical Modelling Electronic Networks Devices and Fields, 2022
    Quantum‐dot Cellular Automata (QCA) lead to fundamental changes in nanoscale technology. It promises small area, low power, & high‐speed structures for digital circuit design. This paper presents efficient low power structures of reversible multiplexer & demultiplexer (RMD) modules based on the QCA technology. The simulation result shows that the proposed RMD module has utilized less area & low power consumption. The simulation, layout, & energy dissipation of the proposed RMD module have been carried out using the QCA Designer‐E simulation tool.
  • VLSI Architecture of Decision Based Adaptive Denoising Filter for removing salt & pepper noise
    Vasudeva Bevara, Bevara Srinu, Pradyut Kumar Sanki
    Ecs Transactions, 2022
    A new Decision Based Adaptive Denoising Filter (DBADF) algorithm & hardware architecture are proposed for restoring the digital image that is highly corrupted with impulse noise. The proposed DBADF detects only the corrupted pixels and that pixel is restored by the noise-free median value or previous value based upon the noise density in the image. The proposed DBADF uses a window initially and adaptively goes up to window based on the noise corruption more than 50% by impulse noise in the current processing window. The proposed architecture was found to exhibit better visual qualitative and quantitative evaluation based on PSNR, IEF, EKI, SSIM, FOM, and error rate. The DBAMF architecture also preserves the original information of digital image with a high density of salt & pepper noise, when compared to many standard conventional algorithms. The proposed architecture has been simulated using the VIRTEX7 FPGA device and the reported maximum post place and route frequency are 149.995MHz and the dynamic power consumption is 179mW.
  • A High-speed Low-power CMOS-Memristor Based Hybrid Comparator Using m-GDI Technique for IoT Applications
    Syed Ali Hussain, P N S B S V Prasad V, Vasudeva Bevara, Pradyut K Sanki
    Proceedings 2022 IEEE International Symposium on Smart Electronic Systems Ises 2022, 2022
    The wearable gadgets facilitate the continuous real-time monitoring of personal health. The VLSI industry is attempting to incorporate more functional modules that run at high speed and consume less power inside the prescribed space. Several methodologies and procedures are designed to implement practical VLSI circuits to meet the market requirements. The Comparator is a basic arithmetic unit in high-end Processors for IoT-based applications. The concept of hybridization facilitates a promising solution to realize high-speed, low-power systems with a minimum number of transistors as compared to the CMOS technology. On the other hand, m_GDI-based logic circuit design is very popular for high-speed & low-power applications. These strategies demonstrate the trade-off between several parameters. In this paper, we have designed a novel CMOS-Memristors-based hybrid 16-bit magnitude compactor using the modified Gate Diffusion Input (m_GDI) technique. The proposed comparator operates at Vdd=1V and offers 12.71nw, 2.44ps, and 31.02zJ of power dissipation, delay, and PDP respectively. All the prescribed circuits have been designed and simulated using a 45nm Generic Process Design Kit (GPDK) in the Cadence Virtuoso tool.
  • VLSI Implementation of a Real-time Modified Decision-based Algorithm for Impulse Noise Removal
    Pradyut Kumar Sanki, Vasudeva Bevara, Medarametla Deepthi Supriya, Devireddy Vignesh, Peram Bhanu Sai Harshath, Siavya Kuchina
    2022 IEEE International Iot Electronics and Mechatronics Conference Iemtronics 2022, 2022
    In this paper, a Real-Time Impulse Noise Removal (RTINR) algorithm and its hardware architecture are proposed for denoising images corrupted with fixed valued impulse noise. A decision-based algorithm is modified in the proposed RTINR algorithm where the corrupted pixel is first detected & is restored with median or previous pixel value depending on the number of corrupted pixels in the image. The proposed RTINR architecture has been designed to reduce the hardware complexity as it requires 21 comparators, 4 adders, and 2 line buffers which in turn improve the execution time. The proposed architecture results better in qualitative and quantitative performance in comparison to different denoising schemes while evaluated based on PSNR, IEF, MSE, EKI, SSIM,& FOM. The proposed architecture has been simulated using the VIRTEX7 FPGA device and the reported maximum post place& route frequency is 360.88 MHz. The proposed RTINR architecture is capable of denoising images of size 512 × 512 at a frame rate of 686. The architecture has also been synthesized using UMC 90 nm technology where 103 mW power is consumed at a clock frequency of 100 MHz with a gate count of 2.3K (NAND2) including two memory buffers.
  • An Ultra-Low Power Reversible MUX and DEMUX using QCA nanotechnology with energy dissipation
    Vasudeva Bevara, Pradyut K Sanki
    Proceedings 2021 IEEE International Symposium on Smart Electronic Systems Ises 2021, 2021
    With the rapid development of Very Large-Scale Integration (VLSI) technology, it is important to achieve a robust design with low power consumption. CMOS design has been affected by several problems over the past few years. Increasing the dissipation of power is a major problem in CMOS devices and circuits. Reversible computing can solve this issue, and reversible logic circuits serve as the foundation of quantum computing. Quantum-dot Cellular Automata (QCA) can be such a nanoscale technology and thus emerges as a promising alternative to the traditional CMOS VLSI. This work focuses on the design of a reversible multiplexer and demultiplexer in the quantum dot cell automata (QCA) framework. Experimentation reveals that the new reversible mux and demux is superior to the traditional reversible modules. The simulation, layout & energy dissipation of the proposed RMD, RM module has been carried out using the QCA Designer-E simulation tool.
  • VLSI implementation of high throughput parallel pipeline median finder for IoT applications
    Vasudeva Bevara, Pradyut Kumar Sanki
    Sadhana Academy Proceedings in Engineering Sciences, 2020
  • A new fast and efficient 2-D median filter architecture
    Vasudeva Bevara, Pradyut Kumar Sanki
    Sadhana Academy Proceedings in Engineering Sciences, 2020

RECENT SCHOLAR PUBLICATIONS

  • A High-Speed, Low-Power Vedic Multiplier Design Based on the Urdhva Tiryakbhyam Sutra for IoT Applications
    G Divya, K Sowmya, K Meghana, K Nandana, V Bevara
    2026 IEEE Madhya Pradesh Section Conference (MPCON), 713-718 , 2026
    2026
  • Low Power and Wide Bandwidth CMOS Active Phase Shifter for X/Ku/K-Band Phased Array Systems
    R Daggula, V Bevara, R Ganapati, S Busi
    Journal of Integrated Circuits and Systems 19 (3), 1-5 , 2024
    2024
  • Optimizing the Threshold Modified Comparator Circuit (TMCC) with NCFET Technology for Low Power and High-Speed Performance
    V Siripurapu, TD Prasad, S Srivallika, V Bevara, SS Surya
    2024 IEEE 16th International Conference on Computational Intelligence and … , 2024
    2024
    Citations: 2
  • An ultra-low power qca based vedic multiplier for digital radar application
    R Daggula, V Bevara
    e-Prime-Advances in Electrical Engineering, Electronics and Energy 9, 100695 , 2024
    2024
    Citations: 8
  • (Digital Presentation) Optimized Security: Enhancing the Modified Advanced Encryption Standard for Efficient Iot Application
    J Naik, H Nyathikala, S Chiluka, V Bevara
    Electrochemical Society Meeting Abstracts 245, 1557-1557 , 2024
    2024
  • Ultra low power reversible arithmetic processor based on QCA
    RVVMKPKA Vasudeva Bevara, Srinu Bevara, Sudhakar Busi
    Optical and Quantum Electronics 56, 586 , 2024
    2024
    Citations: 6
  • Efficient and Enhancing Hardware Security Systems using Quantum‑dot Cellular Automata‑based Substitution Boxes (S‑boxes)
    DRVVMKDNB Dr. Vasudeva Bevara, Chiluka Sagar, Srinu Bevara
    IN Patent App. 202341025190 A , 2023
    2023
  • High‐speed, high‐resolution methodology for portable universal radar target‐echo simulator
    R Daggula, B Vasudeva, M Kamal, A Acharyya
    Microwave and Optical Technology Letters 65 (2), 486-492 , 2023
    2023
    Citations: 6
  • RF choke based methodology for flange effect mitigation and antenna isolation improvement in bistatic radars of aerospace vehicles
    R Daggula, V Bevara, SSR Kumbha, A Acharyya
    AEU-International Journal of Electronics and Communications 159, 154451 , 2023
    2023
    Citations: 1
  • Design of an efficient QCA-based median filter with energy dissipation analysis: V. Bevara et al.
    V Bevara, S Alihussain, P Prasad, PK Sanki
    The Journal of Supercomputing 79 (3), 2984-3004 , 2023
    2023
    Citations: 6
  • A high-speed low-power CMOS-memristor based hybrid comparator using m_GDI technique for IoT applications
    SA Hussain, V Bevara, PK Sanki
    2022 IEEE International Symposium on Smart Electronic Systems (iSES), 631-634 , 2022
    2022
    Citations: 4
  • A Universal Logic Gate Circuit
    PKS Syed Ali Hussain, Bevara Vasudeva, Vemuru PurrnaPrasad
    IN Patent App. 202,241,051,559 , 2022
    2022
  • Piezoelectric Sensor & a Method for its Preparation
    PMPKS Vemuru PurrnaPrasad, K. NagaMalleswari, Bevara Vasudeva, Syed Ali Hussai
    IN Patent App. 202,241,034,906 , 2022
    2022
  • VLSI Implementation of a Real-time Modified Decision-based Algorithm for Impulse Noise Removal
    PK Sanki, V Bevara, MD Supriya, D Vignesh, PBS Harshath, S Kuchina
    2022 IEEE International IOT, Electronics and Mechatronics Conference … , 2022
    2022
    Citations: 2
  • VLSI architecture of decision based adaptive denoising filter for removing salt & pepper noise
    V Bevara, B Srinu, P Kumar Sanki
    Electrochemical Society Transactions 107 (1), 18423-18434 , 2022
    2022
    Citations: 6
  • An ultra-low power reversible mux and demux using qca nanotechnology with energy dissipation
    V Bevara, PK Sanki
    2021 IEEE International Symposium on Smart Electronic Systems (iSES), 323-326 , 2021
    2021
    Citations: 3
  • A novel hardware architecture of Decision Based Adaptive Denoising Algorithm for removing salt & pepper noise
    V BEVARA, PK Sanki, S Bevara
    SGS-Engineering & Sciences 1 (01) , 2021
    2021
  • Design of Efficient Median Filter in Quantum-dot Cellular Automata with Energy Dissipation
    V BEVARA, PK SANKI
    SGS-Engineering & Sciences 1 (01) , 2021
    2021
  • A new fast and efficient 2-D median filter architecture
    V Bevara, PK Sanki
    Sādhanā 45 (1), 192 , 2020
    2020
    Citations: 8
  • VLSI implementation of high throughput parallel pipeline median finder for IoT applications
    V Bevara, PK Sanki
    Sādhanā 45 (1), 75 , 2020
    2020
    Citations: 11

MOST CITED SCHOLAR PUBLICATIONS

  • VLSI implementation of high throughput parallel pipeline median finder for IoT applications
    V Bevara, PK Sanki
    Sādhanā 45 (1), 75 , 2020
    2020.0
    Citations: 11
  • An ultra-low power qca based vedic multiplier for digital radar application
    R Daggula, V Bevara
    e-Prime-Advances in Electrical Engineering, Electronics and Energy 9, 100695 , 2024
    2024.0
    Citations: 8
  • A new fast and efficient 2-D median filter architecture
    V Bevara, PK Sanki
    Sādhanā 45 (1), 192 , 2020
    2020.0
    Citations: 8
  • Ultra low power reversible arithmetic processor based on QCA
    RVVMKPKA Vasudeva Bevara, Srinu Bevara, Sudhakar Busi
    Optical and Quantum Electronics 56, 586 , 2024
    2024.0
    Citations: 6
  • High‐speed, high‐resolution methodology for portable universal radar target‐echo simulator
    R Daggula, B Vasudeva, M Kamal, A Acharyya
    Microwave and Optical Technology Letters 65 (2), 486-492 , 2023
    2023.0
    Citations: 6
  • Design of an efficient QCA-based median filter with energy dissipation analysis: V. Bevara et al.
    V Bevara, S Alihussain, P Prasad, PK Sanki
    The Journal of Supercomputing 79 (3), 2984-3004 , 2023
    2023.0
    Citations: 6
  • VLSI architecture of decision based adaptive denoising filter for removing salt & pepper noise
    V Bevara, B Srinu, P Kumar Sanki
    Electrochemical Society Transactions 107 (1), 18423-18434 , 2022
    2022.0
    Citations: 6
  • A high-speed low-power CMOS-memristor based hybrid comparator using m_GDI technique for IoT applications
    SA Hussain, V Bevara, PK Sanki
    2022 IEEE International Symposium on Smart Electronic Systems (iSES), 631-634 , 2022
    2022.0
    Citations: 4
  • High performance 2^n: 1: 2^n reversible MUX- DMUX architecture for quantum dot cellular automata
    V Bevara, SN Chowdary, BVS Babu, PK Sanki
    Citations: 4
  • An ultra-low power reversible mux and demux using qca nanotechnology with energy dissipation
    V Bevara, PK Sanki
    2021 IEEE International Symposium on Smart Electronic Systems (iSES), 323-326 , 2021
    2021.0
    Citations: 3
  • Optimizing the Threshold Modified Comparator Circuit (TMCC) with NCFET Technology for Low Power and High-Speed Performance
    V Siripurapu, TD Prasad, S Srivallika, V Bevara, SS Surya
    2024 IEEE 16th International Conference on Computational Intelligence and … , 2024
    2024.0
    Citations: 2
  • VLSI Implementation of a Real-time Modified Decision-based Algorithm for Impulse Noise Removal
    PK Sanki, V Bevara, MD Supriya, D Vignesh, PBS Harshath, S Kuchina
    2022 IEEE International IOT, Electronics and Mechatronics Conference … , 2022
    2022.0
    Citations: 2
  • RF choke based methodology for flange effect mitigation and antenna isolation improvement in bistatic radars of aerospace vehicles
    R Daggula, V Bevara, SSR Kumbha, A Acharyya
    AEU-International Journal of Electronics and Communications 159, 154451 , 2023
    2023.0
    Citations: 1
  • A High-Speed, Low-Power Vedic Multiplier Design Based on the Urdhva Tiryakbhyam Sutra for IoT Applications
    G Divya, K Sowmya, K Meghana, K Nandana, V Bevara
    2026 IEEE Madhya Pradesh Section Conference (MPCON), 713-718 , 2026
    2026.0
  • Low Power and Wide Bandwidth CMOS Active Phase Shifter for X/Ku/K-Band Phased Array Systems
    R Daggula, V Bevara, R Ganapati, S Busi
    Journal of Integrated Circuits and Systems 19 (3), 1-5 , 2024
    2024.0
  • (Digital Presentation) Optimized Security: Enhancing the Modified Advanced Encryption Standard for Efficient Iot Application
    J Naik, H Nyathikala, S Chiluka, V Bevara
    Electrochemical Society Meeting Abstracts 245, 1557-1557 , 2024
    2024.0
  • Efficient and Enhancing Hardware Security Systems using Quantum‑dot Cellular Automata‑based Substitution Boxes (S‑boxes)
    DRVVMKDNB Dr. Vasudeva Bevara, Chiluka Sagar, Srinu Bevara
    IN Patent App. 202341025190 A , 2023
    2023.0
  • A Universal Logic Gate Circuit
    PKS Syed Ali Hussain, Bevara Vasudeva, Vemuru PurrnaPrasad
    IN Patent App. 202,241,051,559 , 2022
    2022.0
  • Piezoelectric Sensor & a Method for its Preparation
    PMPKS Vemuru PurrnaPrasad, K. NagaMalleswari, Bevara Vasudeva, Syed Ali Hussai
    IN Patent App. 202,241,034,906 , 2022
    2022.0
  • A novel hardware architecture of Decision Based Adaptive Denoising Algorithm for removing salt & pepper noise
    V BEVARA, PK Sanki, S Bevara
    SGS-Engineering & Sciences 1 (01) , 2021
    2021.0