Dr. Vasudeva Bevara

RESEARCH, TEACHING, or OTHER INTERESTS

Electrical and Electronic Engineering

Scopus Publications

An ultra-low power QCA based vedic multiplier for digital radar application
Rajender Daggula and Vasudeva Bevara
Elsevier BV



Ultra low power reversible arithmetic processor based on QCA
Vasudeva Bevara, Srinu Bevara, Sudhakar Busi, R. V. V. Murali Krishna, and PramodKumar Aylapogu
Springer Science and Business Media LLC



Optimizing the Threshold Modified Comparator Circuit (TMCC) with NCFET Technology for Low Power and High-Speed Performance
Venu Siripurapu, Thota Durga Prasad, Sailada Srivallika, Vasudeva Bevara, and Sarvisetti Soma Surya
IEEE
Comparators had been a major part in the design of various applications like ADCs, Relaxations Oscillators, Schmitt trigger, and many more. The design of these comparators have been advancing over the passing years. the main parameters considered while designing of the comparator are area, power consumed, delay in comparing and giving us the output. we have designed a TMCC (Threshold modified comparator circuit) using NCFET (Negative capacitance field effect transistor) and its power consumption, area utilization and delay have been calculated. The proposed TMCC using NCFET technology have been designed using 40 nm technology. It consumes an average power of 3.5 pW and the delay is 1.325 ns. The above-mentioned parameters have been reduced to a major amount by using NCFET while compared to the CMOS technology.


RF choke based methodology for flange effect mitigation and antenna isolation improvement in bistatic radars of aerospace vehicles
Rajender Daggula, Vasudeva Bevara, Manisha Kamal K., Samba Siva Rao Kumbha, and Amit Acharyya
Elsevier BV



Design of an efficient QCA-based median filter with energy dissipation analysis
Vasudeva Bevara, Syed Alihussain, P. N. S. B. S. V. Prasad, and Pradyut K. Sanki
Springer Science and Business Media LLC



High performance 2ⁿ:1:2ⁿ reversible MUX/DMUX architecture for quantum dot cellular automata
Vasudeva Bevara, Shakamuri Narendra Chowdary, Bolem Venkata Surendra Babu, and Pradyut Kumar Sanki
Wiley
Quantum‐dot Cellular Automata (QCA) lead to fundamental changes in nanoscale technology. It promises small area, low power, & high‐speed structures for digital circuit design. This paper presents efficient low power structures of reversible multiplexer & demultiplexer (RMD) modules based on the QCA technology. The simulation result shows that the proposed RMD module has utilized less area & low power consumption. The simulation, layout, & energy dissipation of the proposed RMD module have been carried out using the QCA Designer‐E simulation tool.


A High-speed Low-power CMOS-Memristor Based Hybrid Comparator Using m-GDI Technique for IoT Applications
Syed Ali Hussain, P N S B S V Prasad V, Vasudeva Bevara, and Pradyut K Sanki
IEEE
The wearable gadgets facilitate the continuous real-time monitoring of personal health. The VLSI industry is attempting to incorporate more functional modules that run at high speed and consume less power inside the prescribed space. Several methodologies and procedures are designed to implement practical VLSI circuits to meet the market requirements. The Comparator is a basic arithmetic unit in high-end Processors for IoT-based applications. The concept of hybridization facilitates a promising solution to realize high-speed, low-power systems with a minimum number of transistors as compared to the CMOS technology. On the other hand, m_GDI-based logic circuit design is very popular for high-speed & low-power applications. These strategies demonstrate the trade-off between several parameters. In this paper, we have designed a novel CMOS-Memristors-based hybrid 16-bit magnitude compactor using the modified Gate Diffusion Input (m_GDI) technique. The proposed comparator operates at Vdd=1V and offers 12.71nw, 2.44ps, and 31.02zJ of power dissipation, delay, and PDP respectively. All the prescribed circuits have been designed and simulated using a 45nm Generic Process Design Kit (GPDK) in the Cadence Virtuoso tool.


VLSI Architecture of Decision Based Adaptive Denoising Filter for removing salt & pepper noise
Vasudeva Bevara, Bevara Srinu, and Pradyut Kumar Sanki
The Electrochemical Society
A new Decision Based Adaptive Denoising Filter (DBADF) algorithm & hardware architecture are proposed for restoring the digital image that is highly corrupted with impulse noise. The proposed DBADF detects only the corrupted pixels and that pixel is restored by the noise-free median value or previous value based upon the noise density in the image. The proposed DBADF uses a window initially and adaptively goes up to window based on the noise corruption more than 50% by impulse noise in the current processing window. The proposed architecture was found to exhibit better visual qualitative and quantitative evaluation based on PSNR, IEF, EKI, SSIM, FOM, and error rate. The DBAMF architecture also preserves the original information of digital image with a high density of salt & pepper noise, when compared to many standard conventional algorithms. The proposed architecture has been simulated using the VIRTEX7 FPGA device and the reported maximum post place and route frequency are 149.995MHz and the dynamic power consumption is 179mW.


VLSI Implementation of a Real-time Modified Decision-based Algorithm for Impulse Noise Removal
Pradyut Kumar Sanki, Vasudeva Bevara, Medarametla Deepthi Supriya, Devireddy Vignesh, Peram Bhanu Sai Harshath, and Siavya Kuchina
IEEE
In this paper, a Real-Time Impulse Noise Removal (RTINR) algorithm and its hardware architecture are proposed for denoising images corrupted with fixed valued impulse noise. A decision-based algorithm is modified in the proposed RTINR algorithm where the corrupted pixel is first detected & is restored with median or previous pixel value depending on the number of corrupted pixels in the image. The proposed RTINR architecture has been designed to reduce the hardware complexity as it requires 21 comparators, 4 adders, and 2 line buffers which in turn improve the execution time. The proposed architecture results better in qualitative and quantitative performance in comparison to different denoising schemes while evaluated based on PSNR, IEF, MSE, EKI, SSIM,& FOM. The proposed architecture has been simulated using the VIRTEX7 FPGA device and the reported maximum post place& route frequency is 360.88 MHz. The proposed RTINR architecture is capable of denoising images of size 512 × 512 at a frame rate of 686. The architecture has also been synthesized using UMC 90 nm technology where 103 mW power is consumed at a clock frequency of 100 MHz with a gate count of 2.3K (NAND2) including two memory buffers.


An Ultra-Low Power Reversible MUX and DEMUX using QCA nanotechnology with energy dissipation
Vasudeva Bevara and Pradyut K Sanki
IEEE
With the rapid development of Very Large-Scale Integration (VLSI) technology, it is important to achieve a robust design with low power consumption. CMOS design has been affected by several problems over the past few years. Increasing the dissipation of power is a major problem in CMOS devices and circuits. Reversible computing can solve this issue, and reversible logic circuits serve as the foundation of quantum computing. Quantum-dot Cellular Automata (QCA) can be such a nanoscale technology and thus emerges as a promising alternative to the traditional CMOS VLSI. This work focuses on the design of a reversible multiplexer and demultiplexer in the quantum dot cell automata (QCA) framework. Experimentation reveals that the new reversible mux and demux is superior to the traditional reversible modules. The simulation, layout & energy dissipation of the proposed RMD, RM module has been carried out using the QCA Designer-E simulation tool.


A new fast and efficient 2-D median filter architecture
Vasudeva Bevara and Pradyut Kumar Sanki
Springer Science and Business Media LLC



VLSI implementation of high throughput parallel pipeline median finder for IoT applications
Vasudeva Bevara and Pradyut Kumar Sanki
Springer Science and Business Media LLC

RECENT SCHOLAR PUBLICATIONS

Low Power and Wide Bandwidth CMOS Active Phase Shifter for X/Ku/K-Band Phased Array Systems
R Daggula, V Bevara, R Ganapati, S Busi
Journal of Integrated Circuits and Systems 19 (3), 1-5 2024



Optimizing the Threshold Modified Comparator Circuit (TMCC) with NCFET Technology for Low Power and High-Speed Performance
V Siripurapu, TD Prasad, S Srivallika, V Bevara, SS Surya
2024 IEEE 16th International Conference on Computational Intelligence and 2024



An ultra-low power QCA based vedic multiplier for digital radar application
R Daggula, V Bevara
e-Prime-Advances in Electrical Engineering, Electronics and Energy 9, 100695 2024



(Digital Presentation) Optimized Security: Enhancing the Modified Advanced Encryption Standard for Efficient Iot Application
J Naik, H Nyathikala, S Chiluka, V Bevara
Electrochemical Society Meeting Abstracts 245, 1557-1557 2024



Ultra low power reversible arithmetic processor based on QCA
RVVMKPKA Vasudeva Bevara, Srinu Bevara, Sudhakar Busi
Optical and Quantum Electronics 56, 586 2024



Efficient and Enhancing Hardware Security Systems using Quantum‑dot Cellular Automata‑based Substitution Boxes (S‑boxes)
DRVVMKDNB Dr. Vasudeva Bevara, Chiluka Sagar, Srinu Bevara
IN Patent App. 202341025190 A 2023



High‐speed, high‐resolution methodology for portable universal radar target‐echo simulator
R Daggula, B Vasudeva, M Kamal, A Acharyya
Microwave and Optical Technology Letters 65 (2), 486-492 2023



RF choke based methodology for flange effect mitigation and antenna isolation improvement in bistatic radars of aerospace vehicles
R Daggula, V Bevara, SSR Kumbha, A Acharyya
AEU-International Journal of Electronics and Communications 159, 154451 2023



Design of an efficient QCA-based median filter with energy dissipation analysis
V Bevara, S Alihussain, P Prasad, PK Sanki
The Journal of Supercomputing 79 (3), 2984-3004 2023



A high-speed low-power CMOS-memristor based hybrid comparator using m_GDI technique for IoT applications
SA Hussain, V Bevara, PK Sanki
2022 IEEE International Symposium on Smart Electronic Systems (iSES), 631-634 2022



A Universal Logic Gate Circuit
PKS Syed Ali Hussain, Bevara Vasudeva, Vemuru PurrnaPrasad
IN Patent App. 202,241,051,559 2022



Piezoelectric Sensor & a Method for its Preparation
PMPKS Vemuru PurrnaPrasad, K. NagaMalleswari, Bevara Vasudeva, Syed Ali Hussai
IN Patent App. 202,241,034,906 2022



VLSI Implementation of a Real-time Modified Decision-based Algorithm for Impulse Noise Removal
PK Sanki, V Bevara, MD Supriya, D Vignesh, PBS Harshath, S Kuchina
2022 IEEE International IOT, Electronics and Mechatronics Conference 2022



VLSI architecture of decision based adaptive denoising filter for removing salt & pepper noise
V Bevara, B Srinu, PK Sanki
ECS transactions 107 (1), 18423 2022



An ultra-low power reversible mux and demux using qca nanotechnology with energy dissipation
V Bevara, PK Sanki
2021 IEEE International Symposium on Smart Electronic Systems (iSES), 323-326 2021



A novel hardware architecture of Decision Based Adaptive Denoising Algorithm for removing salt & pepper noise
V BEVARA, PK Sanki, S Bevara
SGS-Engineering & Sciences 1 (01) 2021



Design of Efficient Median Filter in Quantum-dot Cellular Automata with Energy Dissipation
V BEVARA, PK SANKI
SGS-Engineering & Sciences 1 (01) 2021



A new fast and efficient 2-D median filter architecture
V Bevara, PK Sanki
Sādhanā 45 (1), 192 2020



VLSI implementation of high throughput parallel pipeline median finder for IoT applications
V Bevara, PK Sanki
Sādhanā 45 (1), 75 2020



CMOS and QCA Based Hardware Architecture for Impulse Noise Reduction in Image
B Vasudeva
Mangalagiri

MOST CITED SCHOLAR PUBLICATIONS

VLSI architecture of decision based adaptive denoising filter for removing salt & pepper noise
V Bevara, B Srinu, PK Sanki
ECS transactions 107 (1), 18423 2022
Citations: 6



VLSI implementation of high throughput parallel pipeline median finder for IoT applications
V Bevara, PK Sanki
Sādhanā 45 (1), 75 2020
Citations: 6



A new fast and efficient 2-D median filter architecture
V Bevara, PK Sanki
Sādhanā 45 (1), 192 2020
Citations: 5



High‐speed, high‐resolution methodology for portable universal radar target‐echo simulator
R Daggula, B Vasudeva, M Kamal, A Acharyya
Microwave and Optical Technology Letters 65 (2), 486-492 2023
Citations: 4



Ultra low power reversible arithmetic processor based on QCA
RVVMKPKA Vasudeva Bevara, Srinu Bevara, Sudhakar Busi
Optical and Quantum Electronics 56, 586 2024
Citations: 3



An ultra-low power reversible mux and demux using qca nanotechnology with energy dissipation
V Bevara, PK Sanki
2021 IEEE International Symposium on Smart Electronic Systems (iSES), 323-326 2021
Citations: 3



High performance 2^n: 1: 2^n reversible MUX- DMUX architecture for quantum dot cellular automata
V Bevara, SN Chowdary, BVS Babu, PK Sanki

Citations: 3



Design of an efficient QCA-based median filter with energy dissipation analysis
V Bevara, S Alihussain, P Prasad, PK Sanki
The Journal of Supercomputing 79 (3), 2984-3004 2023
Citations: 2



A high-speed low-power CMOS-memristor based hybrid comparator using m_GDI technique for IoT applications
SA Hussain, V Bevara, PK Sanki
2022 IEEE International Symposium on Smart Electronic Systems (iSES), 631-634 2022
Citations: 2



An ultra-low power QCA based vedic multiplier for digital radar application
R Daggula, V Bevara
e-Prime-Advances in Electrical Engineering, Electronics and Energy 9, 100695 2024
Citations: 1



VLSI Implementation of a Real-time Modified Decision-based Algorithm for Impulse Noise Removal
PK Sanki, V Bevara, MD Supriya, D Vignesh, PBS Harshath, S Kuchina
2022 IEEE International IOT, Electronics and Mechatronics Conference 2022
Citations: 1