Babita Jajodia
@assistant professor
Assistant Professor, Department of Electronics and Communication Engineering
Indian Institute of Information Technology, Guwahati
I, Dr. Babita Jajodia, am an Assistant Professor in the Department of Electronics and Communications Engineering (ECE) at the Indian Institute of Information Technology Guwahati (IIITG) working from July 2019. Prior to that, I received the Ph.D. degree in VLSI Design from the Indian Institute of Technology Guwahati (IITG). Following that I worked at the Gauhati University Institute of Science and Technology (GUIST) as a guest faculty. My research interests are on VLSI Design for Digital/Analog/Mixed-Signal Systems and Quantum Computing.
EDUCATION
Mixed-Signal VLSI Design (PhD) from Indian Institute of Technology Guwahati
RESEARCH, TEACHING, or OTHER INTERESTS
Electrical and Electronic Engineering, Hardware and Architecture
Scopus Publications
Scholar Citations
Scholar h-index
Scholar i10-index
Scopus Publications
Saubi Patel, Shubham Singh, Sumit Kumar, Monalisa Das, and Babita Jajodia
IEEE
This work presents two methods of hardware implementation of area-time-product (ATP)-optimized four-term Karatsuba multipliers (FTKM) on Field Programmable Gate Arrays (FPGAs). This is done by eliminating the effects of complexity of sub-multiplications present at the intermediate steps of computation. Besides these, hardware implementation of the proposed work suggests that the proposed FTKM multiplication methods (FTKM-I and FTKM-II) performs better in terms of resource utilization and delay minimization compared to other existing state-of-the-art multiplication methods, irrespective of input bit lengths. Hardware implementations of the proposed FTKM methods (FTKM-I and FTKM-II) multiplication architecture are demonstrated on a Virtex-7 FPGA device in Xilinx ISE platform. Here, the hardware implementation of the proposed FTKM multipliers is carried out for 128 bits, 256 bits, 512 bits, and 1024 bits, showcasing advantages in area-time-product (ATP) over previous research. ATP serves as the Figure-of-Merit (FoM) for determining the performance of the design.
Raushan Maharana, Arghya Roy, Sourabh Kumar Singh, Monalisa Das, and Babita Jajodia
IEEE
Efficient multiplication of large integer polynomials is essential in modern cryptographic systems. This research delves into the seven-term Karatsuba multiplication method, renowned for its efficiency but often overlooked due to its intricate sub-multiplications. The study concentrates on implementing both asymmetrical and symmetrical versions of seven-term Karatsuba Multiplication (ASeTKM-I, ASeTKM-II, SSeTKM-I, and SSeTKM-II) to enhance speed and hardware utilization. To assess performance, the Area-Time-Product (ATP) metric is computed and compared against conventional asymmetrical and symmetrical seven-term Karatsuba multiplication techniques (CASeTKM and CSSeTKM), as well as contemporary methodologies. Hardware implementations on Virtex-7 FPGA device in Xilinx ISE platform reveal that the most effective proposed method (ASeTKM-I) surpasses other designs. It exhibits superiority, being 19.443%, 79.728%, 39.632%, 5.346%, 37.796%, 6.720%, and 2.616% better than Direct Multiplication (DM), Traditional Schoolbook Multiplication (Traditional SBM), CASeKTM, PASeKTM-II, CSSeTKM, PSSeTKM-I, and PSSeTKM-II, respectively, for 1024-bit inputs.
Sumit Kumar, Saubi Patel, Shubham Singh, Monalisa Das, and Babita Jajodia
IEEE
This paper focusses on FPGA-based optimized implementations of asymmetrical three-term Karatsuba multiplication (AThTKM) architecture. Two multiplications, AThTKM-I and AThTKM-II, are proposed to implement AThTKM, aimed at enhancing the critical path and circuit area. The performance of the proposed design methods is assessed by computing the Area-Time-Product (ATP) and comparing it with conventional asymmetrical three-term Karatsuba multiplication (CAThTKM) and traditional schoolbook multiplication (SBM). Hardware implementations of both proposed AThTKM multiplication archi-tectures are conducted on Virtex-7 FPGA Board using Xilinx ISE platform. The area-time-product (ATP) performance of the proposed AThTKM-I, based on ΔATP1, is better by 22.091%, 80.394%, 32.988%, and 5.277% than Direct Multiplication (DM), Traditional Schoolbook Multiplication (Traditional SBM), and CAThTKM, respectively, for 1024-bit inputs. Similarly, the performance of the proposed AThTKM-II, based on ΔATP2, is better by 17.751%, 79.302%, 29.254%, and -5.571% than Direct Multiplication (DM), Traditional SBM, and CAThTKM, respectively, for 1024-bit inputs. However, comparing both proposed methods of AThTKM (AThTKM-I and AThTKM-II), it can be inferred that AThTKM-II is 0.365%, 3.720%, and 5.277% better than AThTKM-I for 128 bits, 512 bits, and 1024 bits, respectively, while AThTKM-I is 1.080% better than AThTKM-II for 256 bits, respectively, thus demonstrating its area-time-product efficiency.
Raushan Maharana, Sourabh Kumar Singh, Arghya Roy, Monalisa Das, and Babita Jajodia
IEEE
The need for efficient multiplication of large integer polynomials in contemporary cryptographic systems is crucial. This study explores six-term Karatsuba multiplication, known for its efficiency but often avoided due to complex sub-multiplications. The focus is on implementing asymmetrical and symmetrical six-term Karatsuba Multiplication (ASTKM-I, ASTKM-II, SSTKM-I, and SSTKM-II) for enhanced speed and hardware utilization. To evaluate performance, Area-Time-Product (ATP) is calculated and compared with conventional asymmetrical and symmetrical six-term Karatsuba multiplication (CASTKM and CSSTKM) and state-of-the-art approaches. Hardware implementations on a Virtex-7 FPGA device in Xilinx ISE platform show that the best proposed method (ASTKM-II) outperforms other designs, being 17.983%, 79.361 %, 33.439%, 3.536%, 41.494%, 5.975%, and 9.343% better than Direct Multiplication (DM), Traditional Schoolbook Multiplication (Traditional SBM), CASKTM, ASKTM-I, CSSTKM, SSTKM-I, and SSTKM-II, respectively, for 1024-bit inputs.
Jitesh Lalwani, Dana Linnet, Babita Jajodia, Mandaar B. Pande, Amit Patel, Kshitij Dave, and B R Nikilesh
IEEE
Earth observation satellites (EOS) play a crucial role in collecting data for applications like weather forecasting and disaster management. Optimizing EOS missions to capture high-priority targets within constraints such as storage, energy, and weather is challenging for traditional computing methods. Quantum computing shows promise in enhancing efficiency by exploring vast solution spaces for optimal schedules, even with complex constraints. This paper demonstrates the potential of a quantum algorithm to improve real-time EOS mission planning, maximizing high-priority target acquisition under resource limitations. Compared to classical algorithms like simulated annealing and Gurobi optimizer, the proposed quantum algorithm outperformed in selecting high-priority targets by 23.46%, executed faster than Gurobi by 39.09%, and successfully satisfied all constraints for all data.
Shubham Singh, Saubi Patel, Sumit Kumar, Monalisa Das, and Babita Jajodia
IEEE
It is essential to have efficient large integer multiplications for current cryptosystems. Karatsuba-like multiplication is one of the most efficient multiplication algorithms, but is mostly avoided due to complex sub-multiplications. Thus, efforts has been made to implement eight-term Karatsuba Multiplication (Method-II), i.e., ETKM-II in terms of speed and hardware utilization. The overall performance of the proposed design methods are noted by calculating Area-Time-Product (ATP) and compared with conventional eight-term Karatsuba multiplication (CETKM) and existing state-of-the-art. Hardware implementations of the proposed ETKM multiplication architectures are done using Virtex-7 FPGA device in Xilinx ISE platform. Compared with other state-of-the-art designs the performance of the proposed eight-term Karatsuba multiplication (MethodII) based on $\\Delta {ATP}_{2}$ is 13.396%, 78.206% and 38.740% better than Direct Multiplication (DM), Traditional Schoolbook Multiplication (Traditional SBM) and CETKM respectively for 1024bit inputs. However comparing the proposed ETKM-II, it can be inferred that ETKM-II is 38.740% better than CETKM thus proving its area-time-product efficiency.
Raushan Maharana, Monalisa Das, and Babita Jajodia
IEEE
The current demand for efficient multiplication of large integer polynomials in contemporary cryptographic systems is crucial. This work explores the Karatsuba-like multiplication, recognized as one of the most efficient algorithms. Despite its efficiency, this algorithm is often avoided in practice due to the complexity of sub-multiplications during intermediate computation steps. Consequently, efforts have been directed towards implementing asymmetrical and symmetrical five-term Karatsuba Multiplication, denoted as: AFiTKM-I, AFiTKM-II, SFiTKM-I and SFiTKM-II, focusing on speed and hardware utilization. To assess the overall performance of these proposed design methods, the Area-Time-Product (ATP) is calculated and compared with conventional asymmetrical and symmetrical five-term Karatsuba multiplication (CAFiTKM and CSFiTKM) and existing state-of-the-art approaches. Hardware implementations of five FiTKM multiplication architectures were executed using a Virtex-7 FPGA device in the Xilinx ISE platform. Comparing the performance of the best proposed five-term Karatsuba multiplication (AFiTKM-II) based on $\\Delta {ATP}$ with other state-of-the-art designs, it is 22.293%, 80.445%, 31.975%, 0.892%, 36.795%, 2.198% and 0.380% better than Direct Multiplication (DM), Traditional Schoolbook Multiplication (Traditional SBM), CAFiKM, AFiKTM-I, CSFiTKM, SFiTKM-I and SFiTKM-II respectively, for 1024-bit inputs.
Sumit Kumar, Saubi Patel, Shubham Singh, Monalisa Das, and Babita Jajodia
IEEE
The demand for efficient large integer polynomial multiplications in present day crypto-systems is the need of the hour. Karatsuba-like multiplication is one of the most efficient multiplication algorithm discussed in this work. However, this algorithm is mostly practically avoided due to the presence of complex sub-multiplications at the intermediate steps of computation. Thus, efforts has been made to implement two-term Karatsuba Multiplication (Method-I & Method-II), i.e., TTKM-I and TTKM-II in terms of speed and hardware utilization. The overall performance of the proposed design methods are also noted by calculating Area-Time-Product (ATP) and compared with conventional two-term Karatsuba multiplication (CTTKM) and existing state-of-the-art. Hardware implementations of both the proposed TTKM multiplication architectures are done using Virtex-7 FPGA device in Xilinx ISE platform. Compared with other state-of-the-art designs the performance of the proposed two-term Karatsuba multiplication (Method-I) based on ΔATP1 is 11.108%, 98.686%, 15.561%, 72.012%, 95.122%. 6.009% and 24.601% better than Direct Multiplication (DM), Karat-suba Direct Multiplication (KDM), Karatsuba Comba Multiplication (KCM), Traditional Schoolbook Multiplication (Traditional SBM), SBM-I, SBM-II and CTTKM respectively for 512-bit inputs. Similarly the performance of the proposed two-term Karatsuba multiplication (Method-II) based on ΔATP2 is 1.790%, 98.544%, 6.407%, 68.978%. 94.593% and 16.427% better than Direct Multiplication (DM), Karatsuba Direct Multiplication (KDM), Karatsuba Comba Multiplication (KCM), Traditional SBM, SBM-I, SBM-II, CTTKM respectively for 512-bit inputs. However comparing both the proposed methods of TTKM (Method-I and Method-II), it can be inferred that TTKM-I is 9.780% better than TTKM-II thus proving its area-time-product efficiency.
Mekala Karthik, Jitesh Lalwani, and Babita Jajodia
IEEE
In order to transmit images and audio securely, the authors present the Quantum Image Teleportation Protocol (QITP) and Quantum Audio Teleportation Protocol (QATP), which utilizes the Quantum Teleportation (QT) technique combined with Huffman Coding. The QITP secures the teleportation of quantum states of an image while simultaneously encrypting and decrypting them using Huffman Coding since it is only possible to recover or decode data if the prefix codes are known. To test their approach, the authors transformed pixels or RGB values from digital images into text, which was then fed into the Huffman Coding Technique. It has the advantage of compressing the entire text, which makes it faster to transmit vast amounts of information. This work also demonstrates the Quantum Audio Teleportation Protocol (QATP) with and without Huffman coding. For proof of concept, experimental evaluations were performed for both suggested QITPs and QATPs (Standard QITP, QITP with Huffman Coding, Standard QATP, QATP with Huffman Coding), using IBM Quantum Assembly Language (IBM QASM) Simulator and real quantum hardware using the Quantum Information Science Kit (Qiskit), a quantum computing platform.
Aman Chandra, Jitesh Lalwani, and Babita Jajodia
IEEE
Quantum Annealing is a heuristic for solving optimization problems that have seen a recent surge in usage owing to the success of D-Wave Systems. This paper aims to find a good heuristic for solving the Electric Vehicle Charger Placement (EVCP) problem, a problem that stands to be very important given the costs of setting up an electric vehicle (EV) charger and the expected surge in electric vehicles across the world. The same problem statement can also be generalized to the optimal placement of any entity in a grid and can be explored for further uses. Finally, the authors introduce a novel heuristic combining Quantum Annealing and Genetic Algorithms to solve the problem. The proposed hybrid approach entails seeding the genetic algorithms with the results of quantum annealing. Experimental results show that this method decreases the minimum distance from Points of Interest (POI) by 42.S9#x0025; compared to vanilla quantum annealing over the sample EVCP datasets.
Mekala Karthik, Jitesh Lalwani, and Babita Jajodia
IEEE
In this work, the authors present Quantum Text Teleportation Protocol (QTTP) that uses Quantum Teleportation (QT) technique and Huffman Coding for secure text transfers. The QTTP enables the teleportation of quantum states of text (for example, email) in a secure manner, while simultaneously encrypting and decrypting them using Huffman Coding since data can only be retrieved or decoded if the prefix codes are known. The Huffman Coding approach offers the benefit of compressing the entire text, resulting in faster transmission of large amounts of information. For proof of concept, the authors experimentally evaluated both of the proposed QTTPs (Standard QTTP and QTTP with Huffman Coding) using Quantum Information Science Kit (Qiskit), a quantum computing platform and simulated on IBM QASM Simulator and on IBM real quantum hardware.
Monalisa Das and Babita Jajodia
IEEE
The requirements of hardware design for large integer polynomial multiplications is the need of the hour in various cryptographic fields involving large computational complexities. Schoolbook multiplication, being a common alternative is presented in this paper for implementation. A highly optimized Schoolbook multiplier is proposed, which is much faster than the traditional ones. The overall performance of the algorithm is evaluated using Area-Time-Product (ATP). Hardware implementation of the proposed schoolbook multiplication architecture is done using Virtex-7 FPGA device in Xilinx ISE platform.
Monalisa Das and Babita Jajodia
IEEE
Modern cryptographic algorithms demand the use and necessity for large integer polynomial multiplications. However for large input operand size of multipliers, the complexity of the hardware design arises in terms of space and time. Thus, in this paper efforts has been made to design an efficient polynomial multiplier by implementing a hybrid Karatsuba multiplication algorithm. The overall performance of the proposed design is measured using Area-Time-Product (ATP). Hardware implementation of the proposed architecture is done using Virtex-7 FPGA device in Xilinx ISE platform.
Vishesh Mishra, Divy Pandey, Saurabh Singh, Sagar Satapathy, Kaustav Goswami, Babita Jajodia, and Dip Sankar Banerjee
IEEE
In recent times, approximate computing has emerged as a promising technique to achieve significant power and energy benefits in computational systems. It is widely employed in fault-tolerant computationally intensive applications that require large arithmetic blocks. Applications such as image processing and machine learning often invoke the Multiply-Accumulate (MAC) unit for convolution operations. This paper proposes a novel architecture for an (unsigned × unsigned) approximate rounding and truncation based MAC unit named ART-MAC. It replaces the accurate multiplier architecture with an approximate multiplier proposed along with this work, thus improving the overall Quality of Results (QoR). The proposed design consumes 35.35% less power and showcases a significant speedup of 1.23 times when compared to the conventional MAC unit. On an average, the ART-MAC consumes 7.44% lesser on-chip area and showcases 13.49% lesser power-delay-product (PDP) compared to existing state-of-the-art designs.
Mansi Thakare and Babita Jajodia
IEEE
This work proposes an efficient and optimized method of binary square root based on Dwandwa Yoga of Ancient Vedic Mathematics feasible for practical and real-time hardware implementations. This work demonstrates the square root of perfect and non-perfect square numbers on the Field Programmable Gate Array (FPGA) platform with an advantage of the reduced combinational delay, low device utilization (no. of slice LUTs) and area-delay product (ADP) over existing state-of-the-art square root architectures. Hardware implementation results of the proposed binary square root architecture are presented for different input-bit lengths (4-bit, 8-bit, and 16bit) on the FPGA platform. Hardware implementation results of 8-bit non-perfect square input with four-bit integer and four-bit fractional bits on Artix7-xc7a350tfbg484-3 FPGA show that the design shows 74.05% reduced no. of Slice LUTs, 46.47% lower combinational delay and 86.109% better area-delay-product (ADP) for the same accuracy with respect to existing reported state-of-the-art literature.
Purvi Das and Babita Jajodia
IEEE
Analog and mixed-signal circuits products often have a lengthy design process and result in sub-optimal designs because analog performance metrics often have trade-offs, which makes the design of analog circuits challenging. This work develops an optimization methodology that integrates Multi-Objective Genetic Algorithm (MOGA) with Simulation Program with Integrated Circuit Emphasis (SPICE) framework to optimize performance metrics and meet the design specifications. Using the proposed MOGA-SPICE framework, the two-stage operational amplifier is demonstrated to achieve target design specifications by optimizing performance metrics or objectives. Utilizing MOGA framework, the two-stage operational amplifier’s objectives are optimized and design specifications are achieved, and the obtained results are integrated into SPICE for circuit verification. The SPICE-obtained performance metrics shows performance metrics in agreement to the desired design specifications (open-loop DC gain, phase margin, unity-gain bandwidth, slew rate, power dissipation and area) and shows better performance in comparison to the existing state-of-the-art literature.
Saurabh Singh, Vishesh Mishra, Sagar Satapathy, Divy Pandey, Kaustav Goswami, Dip Sankar Banerjee, and Babita Jajodia
IEEE
Approximate computing offers the flexibility to trade-off accuracy for computational speed, reduced power consumption, and lesser on-chip area. Such techniques have accumulated extensive attention in recent times as these can be used in most error-resilient applications. Although several approximate adder designs have been proposed in the past, there still exists scope for further improvement. Existing state-of-the-art designs often involve a trade-off between the margin of acceptable error and its Quality of Results (QoR). This paper proposes an approximate adder with higher accuracy and better QoR for error-resilient applications called an efficient reconfigurable carry speculative approximate adder with rectification, or simply EFCSA adder. Its reconfigurable sister version, called REFCSA adder, is inherently reconfigurable, allowing accurate configuration during runtime. The proposed design aims to limit the carry chain’s length in the conventional ripple carry adder (RCA) using a block-based mechanism. EFCSA showcases results that are 12.3x faster than the conventional RCA. On average, the adder is 45.1% more accurate and has 31.97% better power-delay-product (PDP) than several existing state-of-the-art approximate designs.
Divy Pandey, Vishesh Mishra, Saurabh Singh, Sagar Satapathy, Babita Jajodia, and Dip Sankar Banerjee
IEEE
In recent times, approximate computing is widely employed in the design of power-aware hardware architectures. Approximate computing techniques can be used to benefit a major class of error-resilient applications. It has emerged as a computing paradigm that can efficiently cater several popular applications that can tolerate bounded imprecision in results. Applications such as image processing, machine learning, and deep learning extensively use multiplication and addition operations on 8-bit numbers. This work proposes an 8-bit High-Performance Approximate Multiplier (HPAM) for error resilient applications. HPAM is capable of providing significant speedup at application end while simultaneously maintaining high accuracy standards. It is designed the motivation of providing an broad error bound thus making it worthy in catering applications with high accuracy demands as well as low accuracy standards. Additionally, an approximate version of conventional ripple carry adder (RCA), a Segmented Ripple Carry Approximate Adder (SRCA) is also proposed along with this work. To validate the efficacy of the proposed design, its performance is compared with the conventional Wallace tree multiplier and the existing state-of-the-art designs such as TOSAM, DSM, and LETAM. On average, HPAM provides a speedup of 27.08% and 48.06% more accurate results in comparison to the existing state-of-the-art designs.
Palak Yash, Mansi Thakare, and Babita Jajodia
IEEE
This paper proposes an efficient and optimized method of binary multiplication based on Nikhilam Sutra (algo-rithm) of Ancient Vedic Mathematics feasible for practical and real-time hardware implementations. This work demonstrates hardware implementation results of varying input bit-lengths (4-bit, 8-bit, 16-bit, 32-bit, and 64-bit) on Field Programmable Gate Array (FPGA) platform with an advantage of the reduced combinational delay and low device utilization (no. of slice LUTs) over existing alternative multiplication units and state-of-the-art Urdhva Tiriyakbhyam and Nikhilam Sutra-based multiplication architectures. The proposed binary multiplier architecture is also demonstrated on the Virtex-7 (xc7vx485t-3ffg1157) FPGA device. Hardware implementation results on Xilinx Virtex-7 FPGA device for 8 × 8 proposed multiplication unit show that the design consumes 24 slice LUTs and maximum frequency up to 257.1 MHz.
Simran Jakhodia, Divyanshu Singh, and Babita Jajodia
Springer Nature Singapore
Simran Jakhodia and Babita Jajodia
IEEE
Researchers are currently working on computational solutions based on quantum systems to accelerate the speed of complex mathematical models. This work presented how to formulate complex computational problems as a quantum system of linear equations and find solutions using Quantum Linear System Algorithm (QLSA), also called Quantum Harrow-Hassidim-Lloyd (HHL) algorithm. This paper showed experimental evaluation of multiple problem statements (curve-fitting functions, interpolating polynomials) as a quantum system of linear equations that involve computation of Vandermonde matrices as co-efficient matrices on IBM Quantum Information Software Kit for Quantum Computation (QISKit) platform. Along with a few examples demonstrating its evaluation on diagonal, Hermitian, and Non-Hermitian matrices as co-efficient matrices. The fidelity is used as a measure of performance for comparing the accuracy of quantum results with respect to existing classical solutions on IBM QISKit and drawing conclusions from the experimental results. Experimental evaluation shows that the fidelity depends on the sparsity of the input matrices and therefore the results vary depending on those matrices.
Divyanshu Singh, Simran Jakhodia, and Babita Jajodia
Springer Nature Singapore
Mansi Thakare, Palak Yash, Debaleena Chakraborty, and Babita Jajodia
IEEE
Modern computational devices are in need of efficient and optimized hardware architectures with low power and reduced computational complexity. This work presents an efficient and optimized dedicated cube architecture using the proposed modified Yavadunam Sutra Algorithm of Vedic Mathematics. Hardware implementation results of the proposed Vedic cube architecture for input bit-lengths (4-, 8-, 16- and 32-bit) are presented using Field Programmable Gate Array (FPGA) platform. The proposed cubic architecture on modified Yavadunam Sutra outperforms existing state-of-the-art dedicated cube units in terms of combinational delay and area (No. of four-input/slice LUTs) on a FPGA platform. Comparison results of the proposed dedicated cube architecture with reported Vedic cube architectures are also presented.
Jasmine Bajaj and Babita Jajodia
IEEE
With the ever-escalating demand for high-speed and low-power technology, the archetype of Ancient Vedic Mathematics provides a new approach to modern computing systems. Vedic Mathematics in recent years has provided an edge and garnered massive attention in real-time and high-speed modern computing systems. This work presents an efficient and optimized dedicated recursive squaring architecture designed using Urdhva Tiriyakbhyam Sutra and Karatsuba-Ofman algorithm of Ancient Vedic Mathematics and the proposed recursive squaring technique. Hardware implementation results of the proposed recursive squaring architecture for different input bit lengths (4-bit, 8-bit, 16-bit, 32-bit, and 64 bit) are presented on a Field Programmable Gate Array (FPGA) platform. The proposed squaring architecture outperforms reported state-of-the-art dedicated Vedic squaring units in terms of combinational delay and area (No. of LUTs) on an FPGA platform.
Babita Jajodia, Anil Mahanta, and Shaik Rafi Ahamed
Elsevier BV