Vijayalaxmi Kumbhar
@pccoer.com
Assistant Professor, E&TC Engineering
Pimpri Chinchwad College of Engineering & Research, Ravet
RESEARCH, TEACHING, or OTHER INTERESTS
Electrical and Electronic Engineering, Signal Processing, Artificial Intelligence, Engineering
Scopus Publications
Scholar Citations
Scholar h-index
Scopus Publications
Vishakha Badgujar, Aarya Panse, Manali Mohite, Siddhant Bedse, Pranjal Lanjulkar, Vijayalaxmi Kumbhar, Arti Tekade, and Maithili Andhare
IEEE
This paper presents a novel approach to sustainable agriculture, integrating Machine Learning (ML), Deep Learning (DL), and the Internet of Things (IoT). It employs IoT devices with cameras for real-time monitoring of plant health, enabling early detection of diseases and pests. Through disease and pest detection machine learning models, the system provides farmers with timely alerts and tailored solutions via a user-friendly web application. Additionally, an IoT-based spraying mechanism delivers targeted treatments, reducing the overuse of pesticides and promoting sustainability. It provides precision agriculture, offering an efficient solution to enhance crop management and productivity while minimizing environmental impact.
Dnyaneshwar P. Landge
IEEE
Mayur Patil, Tanmay Waware, Atharva Yawalkar, Vijayalaxmi Kumbhar, Maithili Andhare, and Arti Tekade
IEEE
We have discussed about counter-based SAR ADC in this research paper. A significant component of the high-speed application of ADCs is the SARs critical path. ADCs needed for long term and battery-operated applications typically consume relatively less power. Applications requiring low power, moderate resolution, and medium speed is best suited for SAR ADC. Dynamic latch is employed in our ADC to boost performance and achieve low power consumption. We have demonstrated a 45nm CMOS-simulated, 4-bit low power SAR ADC. Utilizing an ADC design with the maximum amount of simplification, which consists of a dynamic latch comparator, in this paper we are primarily focusing on increasing the sampling frequency of the SAR ADC in order to get high conversion rate. The continuous time analogue low pass filter, which is typically used in front of the ADC to avoid aliasing, was also explored in this paper. Active-RC filters and operational transconductance-C filters are investigated and developed. Results from simulations and measurements are offered to illustrate the performance and functionality.
Abhijeet Patil, Shreyas Kapare, Ganesh Shinde, Arti Tekade, Maithili Andhare, and Vijayalaxmi Kumbar
IEEE
Over the past ten years, the field of digital electronics has experienced tremendous expansion, and technology advancement is accelerating daily. This technology needs to be implemented at a rapid pace with a powerful multiplier. This is an important consideration while developing any digital system. A circuit known as a multiplier produces the product of the inputs it receives. Any number of bits can be multiplied by a multiplier in arithmetic and logic circuits. Because the multiplier uses adders to conduct the action of summing partial products, the multiplier's delay time can be decreased by using more sophisticated adders. In order to compare different parameters and evaluate their performances, this article provides a design and implementation of various multipliers with carry look ahead adder.
Maithili Shailesh Andhare, Vijayalaxmi Sandeep Kumbhar, and Arti Avinash Tekade
IEEE
Cybercriminals and hackers are actively pursuing critical city infrastructures that rely on smart "Industrial Internet of Things (IIoT)" devices. Regardless of the fact that it has prompted a number of interests in recent decades, there isn’t an accurate approach for Industrial IoT attack detection. Prior to actually developing an appropriate approach for detecting Industrial IoT attacks, it’s indeed necessary to have knowledge of previous literature works. As a result, a concise and conceptual literature evaluation is conducted in this research work, including the most applicable methodologies dedicated to IIoT attack detection. All of the research papers gathered is from the years 2020 to 2022. Furthermore, each of the gathered publications is examined in terms of a variety of criteria, including the information source, attack detection methodologies, and performance metrics. Finally, current study gaps in the literature have been highlighted, and this will serve as a benchmark for future IIoT threat detection researchers.
Vijayalaxmi Kumbar and Manisha Waje
FOREX Publication
FinFETs are widely used as efficient alternatives to the single gate general transistor in technology scaling because of their narrow channel characteristic. The width quantization of the FinFET devices helps to reduce the design flexibility of Static Random Access Memory (SRAM) and tackles the design divergence between stable, write and read operations. SRAM is widely used in many medical applications due to its low power consumption but traditional 6T SRAM has short channel effect problems. Recently, to overcome these problems various 7T, 9T, 12T, and 14T SRAM architectures are designed using FinFET. This article provides a comprehensive survey of various designs of SRAM using FinFET. It offers a comparative analysis of FinFET technology, power consumption, propagation delay, power delay product, read and write margin. Additionally, the article presents the simulation of the 5T and 6T SRAM design using CMOS and FinFET for 14 nm technology using Microwind 3.8 simulation tool. The outcomes of the proposed SRAM design are compared with several recent designs based on power, delay, and, and various stability analysis parameters such as read, write and hold noise margin. Finally, the article discusses the challenges in SRAM design using FinFET and provides the future direction for optimization of accuracy, area, speed, delay, and cost of the FinFET-based SRAMs.
Vijayalaxmi Kumbar and Manisha Waje
IEEE
The short-channel effect (SCE) limits the performance of planar MOSFET devices in conventional complementary metal oxide semiconductor (CMOS) technologies due to the ongoing scaling (SCE). FinFETs, Nanowire, and Nanosheet devices are examples of multi-gate FETs (MuG-FETs), which have emerged as the most promising method for extending CMOS scaling past sub-22 nm technology. One of the crucial parts of CPUs is SRAM. This paper provides a comparative analysis of various SRAM designs using CMOS and FinFET devices. The performance of SRAM design is evaluated using propagation delay, power dissipation, and power delay product (PDP).
Vijayalaxmi Kumbar and Vaishali Raut
Springer Nature Singapore