Mohammed Zakir Hussain

@mjcollege.ac.in

Assistant Professor and ECE
Muffakham Jah College of Engineering and Technology

Mohammed Zakir Hussain


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https://researchid.co/zakirhussain
7

Scopus Publications

33

Scholar Citations

2

Scholar h-index

2

Scholar i10-index

Scopus Publications

  • Low power and high performance FFT with different radices
    Md. Zakir Hussain, Kazi Nikhat Parvin
    International Journal of Reconfigurable and Embedded Systems, 2019
    <p>FFT is one of the most active blocks in digital signal processing and in various field of communication systems. FFT has received significant attention over the past years to increase its capability and versatility. This paper describes an extensive study on trade-off of different radices with different computational elements of butterfly such as adders and multipliers. Finding an efficient radix along with computational elements is the key point to find best suite i.e. high precision, low power and low area applications like radar, filtering, image compression etc. The work also considers the precision and the data format to represent constant value such as Q-point. The proposed FFT architectures not only uphold better solutions for low power and high-performance application systems, but also open up a new research lines. This paper demonstrates that radix-2^3 consumes 43% less LUTs and 17% less power consumption, 40% increase of frequency in radix-2^2 in comparison with radix- 2 algorithm for the combination of CSA with modified booth multiplier and the increment of frequency about 19%, 26% less LUTs consumption and 26% less power in Radix-2^2 when compared to radix-4 with various combination of adder and multiplier. In this work we have used Xilinx 14.7 XST for synthesis and the target device used is Spartan6 XC6SLX100. Simulation is carried out in Xilinx ISIM and also performed timing analysis and generated post-place and route.</p>
  • Impact of radices for the design of efficient FFT processor
    Kazi Nikhat Parvin, Md. Zakir Hussain
    Proceedings of the 2nd International Conference on Inventive Systems and Control Icisc 2018, 2018
    Fast Fourier transform (FFT) is always an accepted topic for research from past many years for different applications in digital system. Implementation of FFT processor is an active growing field with possible advances. This work focuses on datapath unit of a FFT processor and presents low complexity and less area consuming datapath unit of FFT by combining algorithms, arithmetic and architecture. Implementation of radix-2, radix-4 and radix-2⁁2 FFT algorithm will be done using different types of multipliers such as Array multiplier, Vedic multiplier and different type of adders like Ripple carry adder and Carry save adder which are represented in fixed point (Q-format) for N=8, 16 points. Synthesize is done to know the performance of LUTs, delay (ns) and Frequency (MHZ) of different radices. Simulation is performed using Verilog code on Spartan6 family. Xilinx ISE 14.7.
  • Multiplication techniques for an efficient FIR filter design for hearing aid applications
    Kazi Nikhat Parvin, Md. Zakir Hussain
    Proceedings of the 2nd International Conference on Inventive Systems and Control Icisc 2018, 2018
    This study represents designing and implementation of a Low pass Finite Impulse Response(FIR) filter of order 10. The set of frequencies utilized are that of a hearing aid. To optimise filter area different multiplication techniques such as constant multiplier, booth multiplier, modified booth multiplier and vedic multiplier have been used to multiply filter coefficient with the input sequence. Adders such as Ripple carry adder, carry save adder, carry look ahead adders have been used to add the product terms. A comparision is made between two different structures, to know the best structure. The Finite Impulse Response(FIR) filter is designed in MATLAB using equirriple method the same is synthesised on xilinx 14.7, spartan 3E XC3S500E whose simulation and synthesis results have been incorporated in the paper.
  • Impact of datapath unit for an efficient implementation of FFT processor
    Kazi Nikhat Parvin, Md. Zakir Hussain, Md. Ali Ghazi Islam
    2017 International Conference on Energy Communication Data Analytics and Soft Computing Icecds 2017, 2018
    Fast Fourier transform (FFT) is always an accepted topic for research from past many years for different applications in the digital system. The computational unit of FFT consists butterfly units which have complex multiplication and complex addition. As multipliers are the basic computational element and also the slow and power consuming element in the processor special multipliers are used to overcome the downside. In this study, we have proposed a computationally efficient Fast Fourier Transform (FFT) based on radix-2 and radix-4 decimation in frequency algorithm, where different multipliers are carried out in FFT algorithm and parameters are compared. This entire work is performed on Xilinx ISE 14.7 and implemented on FPGA Xilinx vertex6 xc6vlx760-2ff1760.
  • High precision arithmetic unit for biomedical and radar system applications
    Kazi Nikhat Parvin, Md. Zakir Hussain, Md. Ali Ghazi Islam
    2017 International Conference on Networks and Advances in Computational Technologies Netact 2017, 2017
    This paper presents a floating point arithmetic modules which are useful for many real time applications such as FFT processor where complex butterfly operations are performed, in which precision and accuracy play a pivotal role in bio-medical and signal processing applications. When compared to fixed point representation, floating point arithmetic provides high precision which helps in increasing the accuracy. This proposed work reduces delay, area and power. Post place and route simulation results have been performed using Xilinx PAR tool on the device Virtex-5 XC5VLX50T — FFl136 and results are proven to be more efficient.
  • Q-point constant multipliers for FFT processors
    Md. Zakir Hussain, Kazi Nikhat Parvin, Zeba Fatima Mir Ilyas Ali
    International Conference on Signal Processing Communication Power and Embedded System Scopes 2016 Proceedings, 2017
    Multiplication of the data with several constants forms the basis for many Digital Signal Processing (DSP) and multimedia applications like in Digital Filtering, in Image Processing DCT and DFT. Most portable devices or handheld devices such as MP3 players, mobile phones, DSLR etc involves large number of multiplications with the several constants. FFT processors also involve large number of complex multiplication operations. As the multiplication operation takes more time they result in an increased delay in the FFT processors with larger area and energy consumption. This paper presents an hardware efficient implementation of the constant multiplier which make use of Q-Format representation to improve the speed of the multipliers as speed plays a crucial role in FFT processors along with Common Subexpression Elimination (CSE) technique and Canonical Signed Digit (CSD) representation to reduce the number of adders hence reduce hardware usage. The design is coded for 8bits, 10 bits and 16 bits fractional fixed point multiplications using Verilog and has been implemented in Altera, device Cyclone IIEP2C35F672C6.
  • Performance efficient FFT processor design
    Md. Zakir Hussain, Kazi Nikhat Parvin, Zeba Fatima Mir Ilyas Ali
    Proceedings International Conference on Global Trends in Signal Processing Information Computing and Communication Icgtspicc 2016, 2017
    This paper proposes a FFT processor design for DAB and WiMAX applications whose efficiency is improved in terms of performance. The design is optimized for power. The 2D 256 point FFT employs Radix-16 algorithm which significantly minimizes the number of complex computations. The architecture is pipelined, with 10 bit real and imaginary inputs. The proposed pipelined FFT architecture has the advantage of reduced computational complexity along with less power consumption. The design makes use of the constant multipliers that were successfully designed and implemented to reduce the hardware complexity and speed was improved to a greater extent when compared with the existing constant multipliers. Compared with the few existing FFT processors, the synthesized results shows that the designed FFT processor reduces the power to a greater extent.

RECENT SCHOLAR PUBLICATIONS

  • Two-stage folded cascode Operational Transconductance Amplifier
    KNPM Mohammed Zakir Hussain
    Journal of Technology 12 (7), 739-746 , 2024
    2024
  • Open-Source EDA Tools for Standard Cell-Based ASIC Design with SkyWater PDK: A Case Study on Approximate and Booth Multipliers
    KNPM Mohammed Zakir Hussain
    Journal of Technology 10 (12) , 2022
    2022
  • Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters
    MZH Kazi Nikhat Parvin
    A Journal of Physical Sciences, Engineering and Technology 12 (No 01), 8-12 , 2020
    2020
  • IMPLEMENTATION OF HIGH-SPEED, LOW-POWER, AND AREA-EFFICIENT FIR FILTERS
    MDZH ARSHAD AHMED TANVIR
    Journal of Engineering Sciences 10 (10), 476-479 , 2019
    2019
  • Impact of Radices for the Design of efficient FFT Processor
    KN Parvin, MZ Hussain
    International Conference on Inventive Systems and Control (ICISC) - IEEE , 2018
    2018
    Citations: 1
  • Multiplication Techniques for an Efficient FIR Filter Design for Hearing aid Applications
    KN Parvin, MZ Hussain
    International Conference on Inventive Systems and Control (ICISC) - IEEE , 2018
    2018
    Citations: 15
  • Multirate Linear Digital Filter Design for Power System Substation
    RKMZ Hussain
    International Conference on Emerging Trends in Engineering, Science and … , 2017
    2017
  • Low Power and Area Efficient Multipliers for Digital Signal Processing
    FSB Md.Zakir Hussain
    International Conference on Emerging Trends in Engineering, Science and … , 2017
    2017
  • Ultra Low Power LFSR For BIST
    MAGIAS Md.Zakir Hussain
    International Conference on Emerging Trends in Engineering, Science and … , 2017
    2017
  • Multirate Linear Digital Filter Design for Power System Substation
    RKMZ Hussain
    International Journal of Advanced Technology in Engineering and Science 5 (03) , 2017
    2017
  • Low Power and Area Efficient Multipliers for Digital Signal Processing
    FSB Md.Zakir Hussain
    International Journal of Advanced Technology in Engineering and Science 5 (03) , 2017
    2017
  • Ultra Low Power LFSR for BIST
    MAGIAS Md.Zakir Hussain
    International Journal of Advanced Technology in Engineering and Science 5 (03) , 2017
    2017
  • IMPACT OF DATAPATH UNIT FOR AN EFFICIENT IMPLEMENTATION OF FFT PROCESSOR
    MAGI Kazi Nikhat Parvin, Md.Zakir Hussain
    International Conference on Energy, Communication, Data Analytics and Soft … , 2017
    2017
    Citations: 1
  • HIGH PRECISION ARITHMETIC UNIT FOR BIOMEDICAL AND RADAR SYSTEM APPLICATIONS
    MAGI Kazi Nikhat Parvin, Md.Zakir Hussain
    International Conference on Networks & Advances in Computational … , 2017
    2017
    Citations: 1
  • Performance efficient FFT processor design
    MZ Hussain, KN Parvin, ZFMI Ali
    2016 International Conference on Global Trends in Signal Processing … , 2016
    2016
    Citations: 2
  • Time-Multiplexed Approach to The Butterfly to reduce Hardware Resource Requirement for FFT
    MZH Md. Ali Gazi Islam
    National Conference on "Emerging Trends in Engineering & Technology" , 2016
    2016
  • Area optimized and frequency efficient 1024 point Radix-2 FFT processor on FPGA
    KNPMZH Md. Ali Ghazi Islam
    International Conference on Communications, Signal Processing, Computing and … , 2016
    2016
  • Performance Efficient FFT Processor Design
    KNPZFMIA Zakir Hussain
    International conference on Global Trends in Signal Processing, Information … , 2016
    2016
  • Q-Point Constant Multipliers for FFT Processors
    KNPZFMIA Zakir Hussain
    International conference on Signal Processing, Communication, Power and … , 2016
    2016
  • A Novel Digital Filter Design for Processing Complex Signal and Implementation on Embedded Hardware for Power System Application
    et al. Md.Zakir Hussain
    National Conference on "Advanced Signal Processing, Embedded & Communication … , 2016
    2016

MOST CITED SCHOLAR PUBLICATIONS

  • Multiplication Techniques for an Efficient FIR Filter Design for Hearing aid Applications
    KN Parvin, MZ Hussain
    International Conference on Inventive Systems and Control (ICISC) - IEEE , 2018
    2018
    Citations: 15
  • Moving Object Detection Based on Background Subtraction & Frame Differencing Technique
    MNU Md.Zakir Hussain,Mrs.Ayesha Naaz
    International Journal of Advanced Research in Computer and Communication … , 2016
    2016
    Citations: 13
  • Performance efficient FFT processor design
    MZ Hussain, KN Parvin, ZFMI Ali
    2016 International Conference on Global Trends in Signal Processing … , 2016
    2016
    Citations: 2
  • Impact of Radices for the Design of efficient FFT Processor
    KN Parvin, MZ Hussain
    International Conference on Inventive Systems and Control (ICISC) - IEEE , 2018
    2018
    Citations: 1
  • IMPACT OF DATAPATH UNIT FOR AN EFFICIENT IMPLEMENTATION OF FFT PROCESSOR
    MAGI Kazi Nikhat Parvin, Md.Zakir Hussain
    International Conference on Energy, Communication, Data Analytics and Soft … , 2017
    2017
    Citations: 1
  • HIGH PRECISION ARITHMETIC UNIT FOR BIOMEDICAL AND RADAR SYSTEM APPLICATIONS
    MAGI Kazi Nikhat Parvin, Md.Zakir Hussain
    International Conference on Networks & Advances in Computational … , 2017
    2017
    Citations: 1
  • Two-stage folded cascode Operational Transconductance Amplifier
    KNPM Mohammed Zakir Hussain
    Journal of Technology 12 (7), 739-746 , 2024
    2024
  • Open-Source EDA Tools for Standard Cell-Based ASIC Design with SkyWater PDK: A Case Study on Approximate and Booth Multipliers
    KNPM Mohammed Zakir Hussain
    Journal of Technology 10 (12) , 2022
    2022
  • Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters
    MZH Kazi Nikhat Parvin
    A Journal of Physical Sciences, Engineering and Technology 12 (No 01), 8-12 , 2020
    2020
  • IMPLEMENTATION OF HIGH-SPEED, LOW-POWER, AND AREA-EFFICIENT FIR FILTERS
    MDZH ARSHAD AHMED TANVIR
    Journal of Engineering Sciences 10 (10), 476-479 , 2019
    2019
  • Multirate Linear Digital Filter Design for Power System Substation
    RKMZ Hussain
    International Conference on Emerging Trends in Engineering, Science and … , 2017
    2017
  • Low Power and Area Efficient Multipliers for Digital Signal Processing
    FSB Md.Zakir Hussain
    International Conference on Emerging Trends in Engineering, Science and … , 2017
    2017
  • Ultra Low Power LFSR For BIST
    MAGIAS Md.Zakir Hussain
    International Conference on Emerging Trends in Engineering, Science and … , 2017
    2017
  • Multirate Linear Digital Filter Design for Power System Substation
    RKMZ Hussain
    International Journal of Advanced Technology in Engineering and Science 5 (03) , 2017
    2017
  • Low Power and Area Efficient Multipliers for Digital Signal Processing
    FSB Md.Zakir Hussain
    International Journal of Advanced Technology in Engineering and Science 5 (03) , 2017
    2017
  • Ultra Low Power LFSR for BIST
    MAGIAS Md.Zakir Hussain
    International Journal of Advanced Technology in Engineering and Science 5 (03) , 2017
    2017
  • Time-Multiplexed Approach to The Butterfly to reduce Hardware Resource Requirement for FFT
    MZH Md. Ali Gazi Islam
    National Conference on "Emerging Trends in Engineering & Technology" , 2016
    2016
  • Area optimized and frequency efficient 1024 point Radix-2 FFT processor on FPGA
    KNPMZH Md. Ali Ghazi Islam
    International Conference on Communications, Signal Processing, Computing and … , 2016
    2016
  • Performance Efficient FFT Processor Design
    KNPZFMIA Zakir Hussain
    International conference on Global Trends in Signal Processing, Information … , 2016
    2016
  • Q-Point Constant Multipliers for FFT Processors
    KNPZFMIA Zakir Hussain
    International conference on Signal Processing, Communication, Power and … , 2016
    2016